1 /* 2 * QEMU SiFive U OTP (One-Time Programmable) Memory interface 3 * 4 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_U_OTP_H 20 #define HW_SIFIVE_U_OTP_H 21 22 #include "hw/sysbus.h" 23 24 #define SIFIVE_U_OTP_PA 0x00 25 #define SIFIVE_U_OTP_PAIO 0x04 26 #define SIFIVE_U_OTP_PAS 0x08 27 #define SIFIVE_U_OTP_PCE 0x0C 28 #define SIFIVE_U_OTP_PCLK 0x10 29 #define SIFIVE_U_OTP_PDIN 0x14 30 #define SIFIVE_U_OTP_PDOUT 0x18 31 #define SIFIVE_U_OTP_PDSTB 0x1C 32 #define SIFIVE_U_OTP_PPROG 0x20 33 #define SIFIVE_U_OTP_PTC 0x24 34 #define SIFIVE_U_OTP_PTM 0x28 35 #define SIFIVE_U_OTP_PTM_REP 0x2C 36 #define SIFIVE_U_OTP_PTR 0x30 37 #define SIFIVE_U_OTP_PTRIM 0x34 38 #define SIFIVE_U_OTP_PWE 0x38 39 40 #define SIFIVE_U_OTP_PWE_EN (1 << 0) 41 42 #define SIFIVE_U_OTP_PCE_EN (1 << 0) 43 44 #define SIFIVE_U_OTP_PDSTB_EN (1 << 0) 45 46 #define SIFIVE_U_OTP_PTRIM_EN (1 << 0) 47 48 #define SIFIVE_U_OTP_PA_MASK 0xfff 49 #define SIFIVE_U_OTP_NUM_FUSES 0x1000 50 #define SIFIVE_U_OTP_FUSE_WORD 4 51 #define SIFIVE_U_OTP_SERIAL_ADDR 0xfc 52 53 #define SIFIVE_U_OTP_REG_SIZE 0x1000 54 55 #define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" 56 57 typedef struct SiFiveUOTPState SiFiveUOTPState; 58 DECLARE_INSTANCE_CHECKER(SiFiveUOTPState, SIFIVE_U_OTP, 59 TYPE_SIFIVE_U_OTP) 60 61 struct SiFiveUOTPState { 62 /*< private >*/ 63 SysBusDevice parent_obj; 64 65 /*< public >*/ 66 MemoryRegion mmio; 67 uint32_t pa; 68 uint32_t paio; 69 uint32_t pas; 70 uint32_t pce; 71 uint32_t pclk; 72 uint32_t pdin; 73 uint32_t pdstb; 74 uint32_t pprog; 75 uint32_t ptc; 76 uint32_t ptm; 77 uint32_t ptm_rep; 78 uint32_t ptr; 79 uint32_t ptrim; 80 uint32_t pwe; 81 uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; 82 uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES]; 83 /* config */ 84 uint32_t serial; 85 BlockBackend *blk; 86 }; 87 88 #endif /* HW_SIFIVE_U_OTP_H */ 89