1 /* 2 * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_E_PRCI_H 20 #define HW_SIFIVE_E_PRCI_H 21 #include "qom/object.h" 22 23 enum { 24 SIFIVE_E_PRCI_HFROSCCFG = 0x0, 25 SIFIVE_E_PRCI_HFXOSCCFG = 0x4, 26 SIFIVE_E_PRCI_PLLCFG = 0x8, 27 SIFIVE_E_PRCI_PLLOUTDIV = 0xC 28 }; 29 30 enum { 31 SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31), 32 SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30) 33 }; 34 35 enum { 36 SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31), 37 SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30) 38 }; 39 40 enum { 41 SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16), 42 SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17), 43 SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18), 44 SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31) 45 }; 46 47 enum { 48 SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8) 49 }; 50 51 #define SIFIVE_E_PRCI_REG_SIZE 0x1000 52 53 #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" 54 55 typedef struct SiFiveEPRCIState SiFiveEPRCIState; 56 DECLARE_INSTANCE_CHECKER(SiFiveEPRCIState, SIFIVE_E_PRCI, 57 TYPE_SIFIVE_E_PRCI) 58 59 struct SiFiveEPRCIState { 60 /*< private >*/ 61 SysBusDevice parent_obj; 62 63 /*< public >*/ 64 MemoryRegion mmio; 65 uint32_t hfrosccfg; 66 uint32_t hfxosccfg; 67 uint32_t pllcfg; 68 uint32_t plloutdiv; 69 }; 70 71 DeviceState *sifive_e_prci_create(hwaddr addr); 72 73 #endif 74