1 /* 2 * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_E_PRCI_H 20 #define HW_SIFIVE_E_PRCI_H 21 22 #include "hw/sysbus.h" 23 24 enum { 25 SIFIVE_E_PRCI_HFROSCCFG = 0x0, 26 SIFIVE_E_PRCI_HFXOSCCFG = 0x4, 27 SIFIVE_E_PRCI_PLLCFG = 0x8, 28 SIFIVE_E_PRCI_PLLOUTDIV = 0xC 29 }; 30 31 enum { 32 SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31), 33 SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30) 34 }; 35 36 enum { 37 SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31), 38 SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30) 39 }; 40 41 enum { 42 SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16), 43 SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17), 44 SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18), 45 SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31) 46 }; 47 48 enum { 49 SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8) 50 }; 51 52 #define SIFIVE_E_PRCI_REG_SIZE 0x1000 53 54 #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" 55 56 typedef struct SiFiveEPRCIState SiFiveEPRCIState; 57 DECLARE_INSTANCE_CHECKER(SiFiveEPRCIState, SIFIVE_E_PRCI, 58 TYPE_SIFIVE_E_PRCI) 59 60 struct SiFiveEPRCIState { 61 /*< private >*/ 62 SysBusDevice parent_obj; 63 64 /*< public >*/ 65 MemoryRegion mmio; 66 uint32_t hfrosccfg; 67 uint32_t hfxosccfg; 68 uint32_t pllcfg; 69 uint32_t plloutdiv; 70 }; 71 72 DeviceState *sifive_e_prci_create(hwaddr addr); 73 74 #endif 75