11e943c58SHao Wu /* 21e943c58SHao Wu * Nuvoton NPCM7xx PWM Module 31e943c58SHao Wu * 41e943c58SHao Wu * Copyright 2020 Google LLC 51e943c58SHao Wu * 61e943c58SHao Wu * This program is free software; you can redistribute it and/or modify it 71e943c58SHao Wu * under the terms of the GNU General Public License as published by the 81e943c58SHao Wu * Free Software Foundation; either version 2 of the License, or 91e943c58SHao Wu * (at your option) any later version. 101e943c58SHao Wu * 111e943c58SHao Wu * This program is distributed in the hope that it will be useful, but WITHOUT 121e943c58SHao Wu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 131e943c58SHao Wu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 141e943c58SHao Wu * for more details. 151e943c58SHao Wu */ 161e943c58SHao Wu #ifndef NPCM7XX_PWM_H 171e943c58SHao Wu #define NPCM7XX_PWM_H 181e943c58SHao Wu 191e943c58SHao Wu #include "hw/clock.h" 201e943c58SHao Wu #include "hw/sysbus.h" 211e943c58SHao Wu #include "hw/irq.h" 221e943c58SHao Wu 231e943c58SHao Wu /* Each PWM module holds 4 PWM channels. */ 241e943c58SHao Wu #define NPCM7XX_PWM_PER_MODULE 4 251e943c58SHao Wu 261e943c58SHao Wu /* 271e943c58SHao Wu * Number of registers in one pwm module. Don't change this without increasing 281e943c58SHao Wu * the version_id in vmstate. 291e943c58SHao Wu */ 301e943c58SHao Wu #define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t)) 311e943c58SHao Wu 321e943c58SHao Wu /* 331e943c58SHao Wu * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY 341e943c58SHao Wu * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty 351e943c58SHao Wu * value of 100,000 the duty cycle for that PWM is 10%. 361e943c58SHao Wu */ 371e943c58SHao Wu #define NPCM7XX_PWM_MAX_DUTY 1000000 381e943c58SHao Wu 391e943c58SHao Wu typedef struct NPCM7xxPWMState NPCM7xxPWMState; 401e943c58SHao Wu 411e943c58SHao Wu /** 421e943c58SHao Wu * struct NPCM7xxPWM - The state of a single PWM channel. 431e943c58SHao Wu * @module: The PWM module that contains this channel. 441e943c58SHao Wu * @irq: GIC interrupt line to fire on expiration if enabled. 451e943c58SHao Wu * @running: Whether this PWM channel is generating output. 461e943c58SHao Wu * @inverted: Whether this PWM channel is inverted. 471e943c58SHao Wu * @index: The index of this PWM channel. 481e943c58SHao Wu * @cnr: The counter register. 491e943c58SHao Wu * @cmr: The comparator register. 501e943c58SHao Wu * @pdr: The data register. 511e943c58SHao Wu * @pwdr: The watchdog register. 521e943c58SHao Wu * @freq: The frequency of this PWM channel. 531e943c58SHao Wu * @duty: The duty cycle of this PWM channel. One unit represents 541e943c58SHao Wu * 1/NPCM7XX_MAX_DUTY cycles. 551e943c58SHao Wu */ 561e943c58SHao Wu typedef struct NPCM7xxPWM { 571e943c58SHao Wu NPCM7xxPWMState *module; 581e943c58SHao Wu 591e943c58SHao Wu qemu_irq irq; 601e943c58SHao Wu 611e943c58SHao Wu bool running; 621e943c58SHao Wu bool inverted; 631e943c58SHao Wu 641e943c58SHao Wu uint8_t index; 651e943c58SHao Wu uint32_t cnr; 661e943c58SHao Wu uint32_t cmr; 671e943c58SHao Wu uint32_t pdr; 681e943c58SHao Wu uint32_t pwdr; 691e943c58SHao Wu 701e943c58SHao Wu uint32_t freq; 711e943c58SHao Wu uint32_t duty; 721e943c58SHao Wu } NPCM7xxPWM; 731e943c58SHao Wu 741e943c58SHao Wu /** 751e943c58SHao Wu * struct NPCM7xxPWMState - Pulse Width Modulation device state. 761e943c58SHao Wu * @parent: System bus device. 771e943c58SHao Wu * @iomem: Memory region through which registers are accessed. 781e943c58SHao Wu * @clock: The PWM clock. 791e943c58SHao Wu * @pwm: The PWM channels owned by this module. 80*71b50b9dSHao Wu * @duty_gpio_out: The duty cycle of each PWM channels as a output GPIO. 811e943c58SHao Wu * @ppr: The prescaler register. 821e943c58SHao Wu * @csr: The clock selector register. 831e943c58SHao Wu * @pcr: The control register. 841e943c58SHao Wu * @pier: The interrupt enable register. 851e943c58SHao Wu * @piir: The interrupt indication register. 861e943c58SHao Wu */ 871e943c58SHao Wu struct NPCM7xxPWMState { 881e943c58SHao Wu SysBusDevice parent; 891e943c58SHao Wu 901e943c58SHao Wu MemoryRegion iomem; 911e943c58SHao Wu 921e943c58SHao Wu Clock *clock; 931e943c58SHao Wu NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE]; 94*71b50b9dSHao Wu qemu_irq duty_gpio_out[NPCM7XX_PWM_PER_MODULE]; 951e943c58SHao Wu 961e943c58SHao Wu uint32_t ppr; 971e943c58SHao Wu uint32_t csr; 981e943c58SHao Wu uint32_t pcr; 991e943c58SHao Wu uint32_t pier; 1001e943c58SHao Wu uint32_t piir; 1011e943c58SHao Wu }; 1021e943c58SHao Wu 1031e943c58SHao Wu #define TYPE_NPCM7XX_PWM "npcm7xx-pwm" 1041e943c58SHao Wu #define NPCM7XX_PWM(obj) \ 1051e943c58SHao Wu OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM) 1061e943c58SHao Wu 1071e943c58SHao Wu #endif /* NPCM7XX_PWM_H */ 108