xref: /openbmc/qemu/include/hw/misc/npcm7xx_gcr.h (revision 5de5b99b)
1 /*
2  * Nuvoton NPCM7xx System Global Control Registers.
3  *
4  * Copyright 2020 Google LLC
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License as published by the
8  * Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14  * for more details.
15  */
16 #ifndef NPCM7XX_GCR_H
17 #define NPCM7XX_GCR_H
18 
19 #include "exec/memory.h"
20 #include "hw/sysbus.h"
21 
22 /*
23  * Number of registers in our device state structure. Don't change this without
24  * incrementing the version_id in the vmstate.
25  */
26 #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
27 
28 typedef struct NPCM7xxGCRState {
29     SysBusDevice parent;
30 
31     MemoryRegion iomem;
32 
33     uint32_t regs[NPCM7XX_GCR_NR_REGS];
34 
35     uint32_t reset_pwron;
36     uint32_t reset_mdlr;
37     uint32_t reset_intcr3;
38 } NPCM7xxGCRState;
39 
40 #define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
41 #define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
42 
43 #endif /* NPCM7XX_GCR_H */
44