1 /* 2 * Nuvoton NPCM7xx Clock Control Registers. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM7XX_CLK_H 17 #define NPCM7XX_CLK_H 18 19 #include "exec/memory.h" 20 #include "hw/sysbus.h" 21 22 /* 23 * The reference clock frequency for the timer modules, and the SECCNT and 24 * CNTR25M registers in this module, is always 25 MHz. 25 */ 26 #define NPCM7XX_TIMER_REF_HZ (25000000) 27 28 /* 29 * Number of registers in our device state structure. Don't change this without 30 * incrementing the version_id in the vmstate. 31 */ 32 #define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) 33 34 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" 35 36 typedef struct NPCM7xxCLKState { 37 SysBusDevice parent; 38 39 MemoryRegion iomem; 40 41 uint32_t regs[NPCM7XX_CLK_NR_REGS]; 42 43 /* Time reference for SECCNT and CNTR25M, initialized by power on reset */ 44 int64_t ref_ns; 45 } NPCM7xxCLKState; 46 47 #define TYPE_NPCM7XX_CLK "npcm7xx-clk" 48 #define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK) 49 50 #endif /* NPCM7XX_CLK_H */ 51