1 /* 2 * QEMU MOS6522 VIA emulation 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #ifndef MOS6522_H 28 #define MOS6522_H 29 30 #include "exec/memory.h" 31 #include "hw/sysbus.h" 32 #include "hw/input/adb.h" 33 #include "qom/object.h" 34 35 #define MOS6522_NUM_REGS 16 36 37 /* Bits in ACR */ 38 #define SR_CTRL 0x1c /* Shift register control bits */ 39 #define SR_EXT 0x0c /* Shift on external clock */ 40 #define SR_OUT 0x10 /* Shift out if 1 */ 41 42 /* Bits in IFR and IER */ 43 #define IER_SET 0x80 /* set bits in IER */ 44 #define IER_CLR 0 /* clear bits in IER */ 45 46 #define CA2_INT_BIT 0 47 #define CA1_INT_BIT 1 48 #define SR_INT_BIT 2 /* Shift register full/empty */ 49 #define CB2_INT_BIT 3 50 #define CB1_INT_BIT 4 51 #define T2_INT_BIT 5 /* Timer 2 interrupt */ 52 #define T1_INT_BIT 6 /* Timer 1 interrupt */ 53 54 #define CA2_INT BIT(CA2_INT_BIT) 55 #define CA1_INT BIT(CA1_INT_BIT) 56 #define SR_INT BIT(SR_INT_BIT) 57 #define CB2_INT BIT(CB2_INT_BIT) 58 #define CB1_INT BIT(CB1_INT_BIT) 59 #define T2_INT BIT(T2_INT_BIT) 60 #define T1_INT BIT(T1_INT_BIT) 61 62 #define VIA_NUM_INTS 5 63 64 /* Bits in ACR */ 65 #define T1MODE 0xc0 /* Timer 1 mode */ 66 #define T1MODE_CONT 0x40 /* continuous interrupts */ 67 68 /* Bits in PCR */ 69 #define CB2_CTRL_MASK 0xe0 70 #define CB2_CTRL_SHIFT 5 71 #define CB1_CTRL_MASK 0x10 72 #define CB1_CTRL_SHIFT 4 73 #define CA2_CTRL_MASK 0x0e 74 #define CA2_CTRL_SHIFT 1 75 #define CA1_CTRL_MASK 0x1 76 #define CA1_CTRL_SHIFT 0 77 78 #define C2_POS 0x2 79 #define C2_IND 0x1 80 81 #define C1_POS 0x1 82 83 /* VIA registers */ 84 #define VIA_REG_B 0x00 85 #define VIA_REG_A 0x01 86 #define VIA_REG_DIRB 0x02 87 #define VIA_REG_DIRA 0x03 88 #define VIA_REG_T1CL 0x04 89 #define VIA_REG_T1CH 0x05 90 #define VIA_REG_T1LL 0x06 91 #define VIA_REG_T1LH 0x07 92 #define VIA_REG_T2CL 0x08 93 #define VIA_REG_T2CH 0x09 94 #define VIA_REG_SR 0x0a 95 #define VIA_REG_ACR 0x0b 96 #define VIA_REG_PCR 0x0c 97 #define VIA_REG_IFR 0x0d 98 #define VIA_REG_IER 0x0e 99 #define VIA_REG_ANH 0x0f 100 101 /** 102 * MOS6522Timer: 103 * @counter_value: counter value at load time 104 */ 105 typedef struct MOS6522Timer { 106 int index; 107 uint16_t latch; 108 uint16_t counter_value; 109 int64_t load_time; 110 int64_t next_irq_time; 111 uint64_t frequency; 112 QEMUTimer *timer; 113 } MOS6522Timer; 114 115 /** 116 * MOS6522State: 117 * @b: B-side data 118 * @a: A-side data 119 * @dirb: B-side direction (1=output) 120 * @dira: A-side direction (1=output) 121 * @sr: Shift register 122 * @acr: Auxiliary control register 123 * @pcr: Peripheral control register 124 * @ifr: Interrupt flag register 125 * @ier: Interrupt enable register 126 * @anh: A-side data, no handshake 127 * @last_b: last value of B register 128 * @last_acr: last value of ACR register 129 */ 130 struct MOS6522State { 131 /*< private >*/ 132 SysBusDevice parent_obj; 133 /*< public >*/ 134 135 MemoryRegion mem; 136 /* VIA registers */ 137 uint8_t b; 138 uint8_t a; 139 uint8_t dirb; 140 uint8_t dira; 141 uint8_t sr; 142 uint8_t acr; 143 uint8_t pcr; 144 uint8_t ifr; 145 uint8_t ier; 146 147 MOS6522Timer timers[2]; 148 uint64_t frequency; 149 150 qemu_irq irq; 151 uint8_t last_irq_levels; 152 }; 153 154 #define TYPE_MOS6522 "mos6522" 155 OBJECT_DECLARE_TYPE(MOS6522State, MOS6522DeviceClass, MOS6522) 156 157 struct MOS6522DeviceClass { 158 DeviceClass parent_class; 159 160 DeviceReset parent_reset; 161 void (*portB_write)(MOS6522State *dev); 162 void (*portA_write)(MOS6522State *dev); 163 /* These are used to influence the CUDA MacOS timebase calibration */ 164 uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti); 165 uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti); 166 uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti); 167 uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti); 168 }; 169 170 171 extern const VMStateDescription vmstate_mos6522; 172 173 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size); 174 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size); 175 176 void hmp_info_via(Monitor *mon, const QDict *qdict); 177 178 #endif /* MOS6522_H */ 179