xref: /openbmc/qemu/include/hw/misc/mips_cmgcr.h (revision 08944be1)
13994215dSYongbok Kim /*
23994215dSYongbok Kim  * This file is subject to the terms and conditions of the GNU General Public
33994215dSYongbok Kim  * License.  See the file "COPYING" in the main directory of this archive
43994215dSYongbok Kim  * for more details.
53994215dSYongbok Kim  *
63994215dSYongbok Kim  * Copyright (C) 2015 Imagination Technologies
73994215dSYongbok Kim  *
83994215dSYongbok Kim  */
93994215dSYongbok Kim 
10121d0712SMarkus Armbruster #ifndef MIPS_CMGCR_H
11121d0712SMarkus Armbruster #define MIPS_CMGCR_H
123994215dSYongbok Kim 
133994215dSYongbok Kim #define TYPE_MIPS_GCR "mips-gcr"
143994215dSYongbok Kim #define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)
153994215dSYongbok Kim 
163994215dSYongbok Kim #define GCR_BASE_ADDR           0x1fbf8000ULL
173994215dSYongbok Kim #define GCR_ADDRSPACE_SZ        0x8000
183994215dSYongbok Kim 
193994215dSYongbok Kim /* Offsets to register blocks */
203994215dSYongbok Kim #define MIPS_GCB_OFS        0x0000 /* Global Control Block */
213994215dSYongbok Kim #define MIPS_CLCB_OFS       0x2000 /* Core Local Control Block */
223994215dSYongbok Kim #define MIPS_COCB_OFS       0x4000 /* Core Other Control Block */
233994215dSYongbok Kim #define MIPS_GDB_OFS        0x6000 /* Global Debug Block */
243994215dSYongbok Kim 
253994215dSYongbok Kim /* Global Control Block Register Map */
263994215dSYongbok Kim #define GCR_CONFIG_OFS      0x0000
273994215dSYongbok Kim #define GCR_BASE_OFS        0x0008
283994215dSYongbok Kim #define GCR_REV_OFS         0x0030
2919494f81SLeon Alrae #define GCR_GIC_BASE_OFS    0x0080
302edd5261SLeon Alrae #define GCR_CPC_BASE_OFS    0x0088
3119494f81SLeon Alrae #define GCR_GIC_STATUS_OFS  0x00D0
322edd5261SLeon Alrae #define GCR_CPC_STATUS_OFS  0x00F0
333994215dSYongbok Kim #define GCR_L2_CONFIG_OFS   0x0130
343994215dSYongbok Kim 
353994215dSYongbok Kim /* Core Local and Core Other Block Register Map */
363994215dSYongbok Kim #define GCR_CL_CONFIG_OFS   0x0010
373994215dSYongbok Kim #define GCR_CL_OTHER_OFS    0x0018
38c09199feSLeon Alrae #define GCR_CL_RESETBASE_OFS 0x0020
393994215dSYongbok Kim 
403994215dSYongbok Kim /* GCR_L2_CONFIG register fields */
413994215dSYongbok Kim #define GCR_L2_CONFIG_BYPASS_SHF    20
423994215dSYongbok Kim #define GCR_L2_CONFIG_BYPASS_MSK    ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
433994215dSYongbok Kim 
44*08944be1SPaul Burton /* GCR_BASE register fields */
45*08944be1SPaul Burton #define GCR_BASE_GCRBASE_MSK     0xffffffff8000ULL
46*08944be1SPaul Burton 
4719494f81SLeon Alrae /* GCR_GIC_BASE register fields */
4819494f81SLeon Alrae #define GCR_GIC_BASE_GICEN_MSK   1
4919494f81SLeon Alrae #define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
5019494f81SLeon Alrae #define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK)
5119494f81SLeon Alrae 
522edd5261SLeon Alrae /* GCR_CPC_BASE register fields */
532edd5261SLeon Alrae #define GCR_CPC_BASE_CPCEN_MSK   1
542edd5261SLeon Alrae #define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
552edd5261SLeon Alrae #define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
562edd5261SLeon Alrae 
57c09199feSLeon Alrae /* GCR_CL_OTHER_OFS register fields */
58c09199feSLeon Alrae #define GCR_CL_OTHER_VPOTHER_MSK 0x7
59c09199feSLeon Alrae #define GCR_CL_OTHER_MSK GCR_CL_OTHER_VPOTHER_MSK
60c09199feSLeon Alrae 
61c09199feSLeon Alrae /* GCR_CL_RESETBASE_OFS register fields */
62c09199feSLeon Alrae #define GCR_CL_RESET_BASE_RESETBASE_MSK 0xFFFFF000U
63c09199feSLeon Alrae #define GCR_CL_RESET_BASE_MSK GCR_CL_RESET_BASE_RESETBASE_MSK
64c09199feSLeon Alrae 
65c09199feSLeon Alrae typedef struct MIPSGCRVPState MIPSGCRVPState;
66c09199feSLeon Alrae struct MIPSGCRVPState {
67c09199feSLeon Alrae     uint32_t other;
68c09199feSLeon Alrae     uint64_t reset_base;
69c09199feSLeon Alrae };
70c09199feSLeon Alrae 
713994215dSYongbok Kim typedef struct MIPSGCRState MIPSGCRState;
723994215dSYongbok Kim struct MIPSGCRState {
733994215dSYongbok Kim     SysBusDevice parent_obj;
743994215dSYongbok Kim 
753994215dSYongbok Kim     int32_t gcr_rev;
763994215dSYongbok Kim     int32_t num_vps;
773994215dSYongbok Kim     hwaddr gcr_base;
783994215dSYongbok Kim     MemoryRegion iomem;
792edd5261SLeon Alrae     MemoryRegion *cpc_mr;
8019494f81SLeon Alrae     MemoryRegion *gic_mr;
812edd5261SLeon Alrae 
822edd5261SLeon Alrae     uint64_t cpc_base;
8319494f81SLeon Alrae     uint64_t gic_base;
84c09199feSLeon Alrae 
85c09199feSLeon Alrae     /* VP Local/Other Registers */
86c09199feSLeon Alrae     MIPSGCRVPState *vps;
873994215dSYongbok Kim };
883994215dSYongbok Kim 
89121d0712SMarkus Armbruster #endif /* MIPS_CMGCR_H */
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