1 /* 2 * ARM IoTKit system control element 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the "system control element" which is part of the 14 * Arm IoTKit and documented in 15 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 16 * Specifically, it implements the "system information block" and 17 * "system control register" blocks. 18 * 19 * QEMU interface: 20 * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the 21 * system information block of the SSE 22 * (used to identify whether to provide SSE-200-only registers) 23 * + sysbus MMIO region 0: the system information register bank 24 * + sysbus MMIO region 1: the system control register bank 25 */ 26 27 #ifndef HW_MISC_IOTKIT_SYSCTL_H 28 #define HW_MISC_IOTKIT_SYSCTL_H 29 30 #include "hw/sysbus.h" 31 #include "qom/object.h" 32 33 #define TYPE_IOTKIT_SYSCTL "iotkit-sysctl" 34 typedef struct IoTKitSysCtl IoTKitSysCtl; 35 DECLARE_INSTANCE_CHECKER(IoTKitSysCtl, IOTKIT_SYSCTL, 36 TYPE_IOTKIT_SYSCTL) 37 38 struct IoTKitSysCtl { 39 /*< private >*/ 40 SysBusDevice parent_obj; 41 42 /*< public >*/ 43 MemoryRegion iomem; 44 45 uint32_t secure_debug; 46 uint32_t reset_syndrome; 47 uint32_t reset_mask; 48 uint32_t gretreg; 49 uint32_t initsvtor0; 50 uint32_t cpuwait; 51 uint32_t wicctrl; 52 uint32_t scsecctrl; 53 uint32_t fclk_div; 54 uint32_t sysclk_div; 55 uint32_t clock_force; 56 uint32_t initsvtor1; 57 uint32_t nmi_enable; 58 uint32_t ewctrl; 59 uint32_t pdcm_pd_sys_sense; 60 uint32_t pdcm_pd_sram0_sense; 61 uint32_t pdcm_pd_sram1_sense; 62 uint32_t pdcm_pd_sram2_sense; 63 uint32_t pdcm_pd_sram3_sense; 64 65 /* Properties */ 66 uint32_t sys_version; 67 uint32_t cpuwait_rst; 68 uint32_t initsvtor0_rst; 69 uint32_t initsvtor1_rst; 70 71 bool is_sse200; 72 }; 73 74 #endif 75