1 /* 2 * IMX31 Clock Control Module 3 * 4 * Copyright (C) 2012 NICTA 5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or later. 8 * See the COPYING file in the top-level directory. 9 */ 10 11 #ifndef IMX_CCM_H 12 #define IMX_CCM_H 13 14 #include "hw/sysbus.h" 15 16 /* CCMR */ 17 #define CCMR_FPME (1<<0) 18 #define CCMR_MPE (1<<3) 19 #define CCMR_MDS (1<<7) 20 #define CCMR_FPMF (1<<26) 21 #define CCMR_PRCS (3<<1) 22 23 /* PDR0 */ 24 #define PDR0_MCU_PODF_SHIFT (0) 25 #define PDR0_MCU_PODF_MASK (0x7) 26 #define PDR0_MAX_PODF_SHIFT (3) 27 #define PDR0_MAX_PODF_MASK (0x7) 28 #define PDR0_IPG_PODF_SHIFT (6) 29 #define PDR0_IPG_PODF_MASK (0x3) 30 #define PDR0_NFC_PODF_SHIFT (8) 31 #define PDR0_NFC_PODF_MASK (0x7) 32 #define PDR0_HSP_PODF_SHIFT (11) 33 #define PDR0_HSP_PODF_MASK (0x7) 34 #define PDR0_PER_PODF_SHIFT (16) 35 #define PDR0_PER_PODF_MASK (0x1f) 36 #define PDR0_CSI_PODF_SHIFT (23) 37 #define PDR0_CSI_PODF_MASK (0x1ff) 38 39 #define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \ 40 & PDR0_##name##_PODF_MASK) 41 #define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \ 42 PDR0_##name##_PODF_SHIFT) 43 44 /* PLL control registers */ 45 #define PD(v) (((v) >> 26) & 0xf) 46 #define MFD(v) (((v) >> 16) & 0x3ff) 47 #define MFI(v) (((v) >> 10) & 0xf); 48 #define MFN(v) ((v) & 0x3ff) 49 50 #define PLL_PD(x) (((x) & 0xf) << 26) 51 #define PLL_MFD(x) (((x) & 0x3ff) << 16) 52 #define PLL_MFI(x) (((x) & 0xf) << 10) 53 #define PLL_MFN(x) (((x) & 0x3ff) << 0) 54 55 #define TYPE_IMX_CCM "imx.ccm" 56 #define IMX_CCM(obj) OBJECT_CHECK(IMXCCMState, (obj), TYPE_IMX_CCM) 57 58 typedef struct IMXCCMState { 59 /* <private> */ 60 SysBusDevice parent_obj; 61 62 /* <public> */ 63 MemoryRegion iomem; 64 65 uint32_t ccmr; 66 uint32_t pdr0; 67 uint32_t pdr1; 68 uint32_t mpctl; 69 uint32_t spctl; 70 uint32_t cgr[3]; 71 uint32_t pmcr0; 72 uint32_t pmcr1; 73 74 /* Frequencies precalculated on register changes */ 75 uint32_t pll_refclk_freq; 76 uint32_t mcu_clk_freq; 77 uint32_t hsp_clk_freq; 78 uint32_t ipg_clk_freq; 79 } IMXCCMState; 80 81 typedef enum { 82 NOCLK, 83 MCU, 84 HSP, 85 IPG, 86 CLK_32k 87 } IMXClk; 88 89 uint32_t imx_clock_frequency(DeviceState *s, IMXClk clock); 90 91 #endif /* IMX_CCM_H */ 92