1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 #ifndef ASPEED_SCU_H 12 #define ASPEED_SCU_H 13 14 #include "hw/sysbus.h" 15 16 #define TYPE_ASPEED_SCU "aspeed.scu" 17 #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) 18 19 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 20 21 typedef struct AspeedSCUState { 22 /*< private >*/ 23 SysBusDevice parent_obj; 24 25 /*< public >*/ 26 MemoryRegion iomem; 27 28 uint32_t regs[ASPEED_SCU_NR_REGS]; 29 uint32_t silicon_rev; 30 uint32_t hw_strap1; 31 uint32_t hw_strap2; 32 uint32_t hw_prot_key; 33 34 uint32_t clkin; 35 uint32_t hpll; 36 uint32_t apb_freq; 37 } AspeedSCUState; 38 39 #define AST2400_A0_SILICON_REV 0x02000303U 40 #define AST2400_A1_SILICON_REV 0x02010303U 41 #define AST2500_A0_SILICON_REV 0x04000303U 42 #define AST2500_A1_SILICON_REV 0x04010303U 43 44 extern bool is_supported_silicon_rev(uint32_t silicon_rev); 45 46 #define ASPEED_SCU_PROT_KEY 0x1688A8A8 47 48 /* 49 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 50 * were added. 51 * 52 * Original header file : 53 * arch/arm/mach-aspeed/include/mach/regs-scu.h 54 * 55 * Copyright (C) 2012-2020 ASPEED Technology Inc. 56 * 57 * This program is free software; you can redistribute it and/or modify 58 * it under the terms of the GNU General Public License version 2 as 59 * published by the Free Software Foundation. 60 * 61 * History : 62 * 1. 2012/12/29 Ryan Chen Create 63 */ 64 65 /* SCU08 Clock Selection Register 66 * 67 * 31 Enable Video Engine clock dynamic slow down 68 * 30:28 Video Engine clock slow down setting 69 * 27 2D Engine GCLK clock source selection 70 * 26 2D Engine GCLK clock throttling enable 71 * 25:23 APB PCLK divider selection 72 * 22:20 LPC Host LHCLK divider selection 73 * 19 LPC Host LHCLK clock generation/output enable control 74 * 18:16 MAC AHB bus clock divider selection 75 * 15 SD/SDIO clock running enable 76 * 14:12 SD/SDIO divider selection 77 * 11 Reserved 78 * 10:8 Video port output clock delay control bit 79 * 7 ARM CPU/AHB clock slow down enable 80 * 6:4 ARM CPU/AHB clock slow down setting 81 * 3:2 ECLK clock source selection 82 * 1 CPU/AHB clock slow down idle timer 83 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) 84 */ 85 #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) 86 87 /* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) 88 * 89 * 18 H-PLL parameter selection 90 * 0: Select H-PLL by strapping resistors 91 * 1: Select H-PLL by the programmed registers (SCU24[17:0]) 92 * 17 Enable H-PLL bypass mode 93 * 16 Turn off H-PLL 94 * 10:5 H-PLL Numerator 95 * 4 H-PLL Output Divider 96 * 3:0 H-PLL Denumerator 97 * 98 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)] 99 */ 100 101 #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) 102 #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) 103 #define SCU_AST2400_H_PLL_OFF (0x1 << 16) 104 105 /* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) 106 * 107 * 21 Enable H-PLL reset 108 * 20 Enable H-PLL bypass mode 109 * 19 Turn off H-PLL 110 * 18:13 H-PLL Post Divider 111 * 12:5 H-PLL Numerator (M) 112 * 4:0 H-PLL Denumerator (N) 113 * 114 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) 115 * 116 * The default frequency is 792Mhz when CLKIN = 24MHz 117 */ 118 119 #define SCU_H_PLL_BYPASS_EN (0x1 << 20) 120 #define SCU_H_PLL_OFF (0x1 << 19) 121 122 /* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) 123 * 124 * 31:29 Software defined strapping registers 125 * 28:27 DRAM size setting (for VGA driver use) 126 * 26:24 DRAM configuration setting 127 * 23 Enable 25 MHz reference clock input 128 * 22 Enable GPIOE pass-through mode 129 * 21 Enable GPIOD pass-through mode 130 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 131 * 19 Disable ACPI function 132 * 23,18 Clock source selection 133 * 17 Enable BMC 2nd boot watchdog timer 134 * 16 SuperIO configuration address selection 135 * 15 VGA Class Code selection 136 * 14 Enable LPC dedicated reset pin function 137 * 13:12 SPI mode selection 138 * 11:10 CPU/AHB clock frequency ratio selection 139 * 9:8 H-PLL default clock frequency selection 140 * 7 Define MAC#2 interface 141 * 6 Define MAC#1 interface 142 * 5 Enable VGA BIOS ROM 143 * 4 Boot flash memory extended option 144 * 3:2 VGA memory size selection 145 * 1:0 BMC CPU boot code selection 146 */ 147 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 148 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 149 150 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 151 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 152 #define DRAM_SIZE_64MB 0 153 #define DRAM_SIZE_128MB 1 154 #define DRAM_SIZE_256MB 2 155 #define DRAM_SIZE_512MB 3 156 157 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 158 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 159 160 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 161 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 162 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 163 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 164 165 /* bit 23, 18 [1,0] */ 166 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 167 | (((x) & 0x1) << 18)) 168 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 169 | (((x) >> 18) & 0x1)) 170 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 171 #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) 172 #define AST2400_CLK_24M_IN 0 173 #define AST2400_CLK_48M_IN 1 174 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 175 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 176 177 #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) 178 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 179 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 180 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 181 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 182 183 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 184 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 185 #define SCU_HW_STRAP_SPI_DIS 0 186 #define SCU_HW_STRAP_SPI_MASTER 1 187 #define SCU_HW_STRAP_SPI_M_S_EN 2 188 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 189 190 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 191 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 192 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 193 #define AST2400_CPU_AHB_RATIO_1_1 0 194 #define AST2400_CPU_AHB_RATIO_2_1 1 195 #define AST2400_CPU_AHB_RATIO_4_1 2 196 #define AST2400_CPU_AHB_RATIO_3_1 3 197 198 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 199 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 200 #define AST2400_CPU_384MHZ 0 201 #define AST2400_CPU_360MHZ 1 202 #define AST2400_CPU_336MHZ 2 203 #define AST2400_CPU_408MHZ 3 204 205 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 206 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 207 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 208 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 209 210 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 211 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 212 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 213 #define VGA_8M_DRAM 0 214 #define VGA_16M_DRAM 1 215 #define VGA_32M_DRAM 2 216 #define VGA_64M_DRAM 3 217 218 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 219 #define AST2400_NOR_BOOT 0 220 #define AST2400_NAND_BOOT 1 221 #define AST2400_SPI_BOOT 2 222 #define AST2400_DIS_BOOT 3 223 224 /* 225 * SCU70 Hardware strapping register definition (for Aspeed AST2500 226 * SoC and higher) 227 * 228 * 31 Enable SPI Flash Strap Auto Fetch Mode 229 * 30 Enable GPIO Strap Mode 230 * 29 Select UART Debug Port 231 * 28 Reserved (1) 232 * 27 Enable fast reset mode for ARM ICE debugger 233 * 26 Enable eSPI flash mode 234 * 25 Enable eSPI mode 235 * 24 Select DDR4 SDRAM 236 * 23 Select 25 MHz reference clock input mode 237 * 22 Enable GPIOE pass-through mode 238 * 21 Enable GPIOD pass-through mode 239 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 240 * 19 Enable ACPI function 241 * 18 Select USBCKI input frequency 242 * 17 Enable BMC 2nd boot watchdog timer 243 * 16 SuperIO configuration address selection 244 * 15 VGA Class Code selection 245 * 14 Select dedicated LPC reset input 246 * 13:12 SPI mode selection 247 * 11:9 AXI/AHB clock frequency ratio selection 248 * 8 Reserved (0) 249 * 7 Define MAC#2 interface 250 * 6 Define MAC#1 interface 251 * 5 Enable dedicated VGA BIOS ROM 252 * 4 Reserved (0) 253 * 3:2 VGA memory size selection 254 * 1 Reserved (1) 255 * 0 Disable CPU boot 256 */ 257 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 258 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 259 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 260 #define UART_DEBUG_UART1 0 261 #define UART_DEBUG_UART5 1 262 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 263 264 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 265 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 266 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 267 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 268 269 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 270 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 271 #define USBCKI_FREQ_24MHZ 0 272 #define USBCKI_FREQ_28MHZ 1 273 274 #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 275 #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 276 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 277 #define AXI_AHB_RATIO_UNDEFINED 0 278 #define AXI_AHB_RATIO_2_1 1 279 #define AXI_AHB_RATIO_3_1 2 280 #define AXI_AHB_RATIO_4_1 3 281 #define AXI_AHB_RATIO_5_1 4 282 #define AXI_AHB_RATIO_6_1 5 283 #define AXI_AHB_RATIO_7_1 6 284 #define AXI_AHB_RATIO_8_1 7 285 286 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 287 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 288 289 #define AST2500_HW_STRAP1_DEFAULTS ( \ 290 SCU_AST2500_HW_STRAP_RESERVED28 | \ 291 SCU_HW_STRAP_2ND_BOOT_WDT | \ 292 SCU_HW_STRAP_VGA_CLASS_CODE | \ 293 SCU_HW_STRAP_LPC_RESET_PIN | \ 294 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 295 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 296 SCU_AST2500_HW_STRAP_RESERVED1) 297 298 #endif /* ASPEED_SCU_H */ 299