1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 #ifndef ASPEED_SCU_H 12 #define ASPEED_SCU_H 13 14 #include "hw/sysbus.h" 15 16 #define TYPE_ASPEED_SCU "aspeed.scu" 17 #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) 18 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" 19 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" 20 21 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 22 23 typedef struct AspeedSCUState { 24 /*< private >*/ 25 SysBusDevice parent_obj; 26 27 /*< public >*/ 28 MemoryRegion iomem; 29 30 uint32_t regs[ASPEED_SCU_NR_REGS]; 31 uint32_t silicon_rev; 32 uint32_t hw_strap1; 33 uint32_t hw_strap2; 34 uint32_t hw_prot_key; 35 } AspeedSCUState; 36 37 #define AST2400_A0_SILICON_REV 0x02000303U 38 #define AST2400_A1_SILICON_REV 0x02010303U 39 #define AST2500_A0_SILICON_REV 0x04000303U 40 #define AST2500_A1_SILICON_REV 0x04010303U 41 42 #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) 43 44 extern bool is_supported_silicon_rev(uint32_t silicon_rev); 45 46 #define ASPEED_SCU_CLASS(klass) \ 47 OBJECT_CLASS_CHECK(AspeedSCUClass, (klass), TYPE_ASPEED_SCU) 48 #define ASPEED_SCU_GET_CLASS(obj) \ 49 OBJECT_GET_CLASS(AspeedSCUClass, (obj), TYPE_ASPEED_SCU) 50 51 typedef struct AspeedSCUClass { 52 SysBusDeviceClass parent_class; 53 54 const uint32_t *resets; 55 uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); 56 uint32_t apb_divider; 57 } AspeedSCUClass; 58 59 #define ASPEED_SCU_PROT_KEY 0x1688A8A8 60 61 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); 62 63 /* 64 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 65 * were added. 66 * 67 * Original header file : 68 * arch/arm/mach-aspeed/include/mach/regs-scu.h 69 * 70 * Copyright (C) 2012-2020 ASPEED Technology Inc. 71 * 72 * This program is free software; you can redistribute it and/or modify 73 * it under the terms of the GNU General Public License version 2 as 74 * published by the Free Software Foundation. 75 * 76 * History : 77 * 1. 2012/12/29 Ryan Chen Create 78 */ 79 80 /* SCU08 Clock Selection Register 81 * 82 * 31 Enable Video Engine clock dynamic slow down 83 * 30:28 Video Engine clock slow down setting 84 * 27 2D Engine GCLK clock source selection 85 * 26 2D Engine GCLK clock throttling enable 86 * 25:23 APB PCLK divider selection 87 * 22:20 LPC Host LHCLK divider selection 88 * 19 LPC Host LHCLK clock generation/output enable control 89 * 18:16 MAC AHB bus clock divider selection 90 * 15 SD/SDIO clock running enable 91 * 14:12 SD/SDIO divider selection 92 * 11 Reserved 93 * 10:8 Video port output clock delay control bit 94 * 7 ARM CPU/AHB clock slow down enable 95 * 6:4 ARM CPU/AHB clock slow down setting 96 * 3:2 ECLK clock source selection 97 * 1 CPU/AHB clock slow down idle timer 98 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) 99 */ 100 #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) 101 102 /* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) 103 * 104 * 18 H-PLL parameter selection 105 * 0: Select H-PLL by strapping resistors 106 * 1: Select H-PLL by the programmed registers (SCU24[17:0]) 107 * 17 Enable H-PLL bypass mode 108 * 16 Turn off H-PLL 109 * 10:5 H-PLL Numerator 110 * 4 H-PLL Output Divider 111 * 3:0 H-PLL Denumerator 112 * 113 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)] 114 */ 115 116 #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) 117 #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) 118 #define SCU_AST2400_H_PLL_OFF (0x1 << 16) 119 120 /* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) 121 * 122 * 21 Enable H-PLL reset 123 * 20 Enable H-PLL bypass mode 124 * 19 Turn off H-PLL 125 * 18:13 H-PLL Post Divider 126 * 12:5 H-PLL Numerator (M) 127 * 4:0 H-PLL Denumerator (N) 128 * 129 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) 130 * 131 * The default frequency is 792Mhz when CLKIN = 24MHz 132 */ 133 134 #define SCU_H_PLL_BYPASS_EN (0x1 << 20) 135 #define SCU_H_PLL_OFF (0x1 << 19) 136 137 /* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) 138 * 139 * 31:29 Software defined strapping registers 140 * 28:27 DRAM size setting (for VGA driver use) 141 * 26:24 DRAM configuration setting 142 * 23 Enable 25 MHz reference clock input 143 * 22 Enable GPIOE pass-through mode 144 * 21 Enable GPIOD pass-through mode 145 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 146 * 19 Disable ACPI function 147 * 23,18 Clock source selection 148 * 17 Enable BMC 2nd boot watchdog timer 149 * 16 SuperIO configuration address selection 150 * 15 VGA Class Code selection 151 * 14 Enable LPC dedicated reset pin function 152 * 13:12 SPI mode selection 153 * 11:10 CPU/AHB clock frequency ratio selection 154 * 9:8 H-PLL default clock frequency selection 155 * 7 Define MAC#2 interface 156 * 6 Define MAC#1 interface 157 * 5 Enable VGA BIOS ROM 158 * 4 Boot flash memory extended option 159 * 3:2 VGA memory size selection 160 * 1:0 BMC CPU boot code selection 161 */ 162 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 163 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 164 165 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 166 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 167 #define DRAM_SIZE_64MB 0 168 #define DRAM_SIZE_128MB 1 169 #define DRAM_SIZE_256MB 2 170 #define DRAM_SIZE_512MB 3 171 172 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 173 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 174 175 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 176 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 177 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 178 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 179 180 /* bit 23, 18 [1,0] */ 181 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 182 | (((x) & 0x1) << 18)) 183 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 184 | (((x) >> 18) & 0x1)) 185 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 186 #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) 187 #define AST2400_CLK_24M_IN 0 188 #define AST2400_CLK_48M_IN 1 189 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 190 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 191 192 #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) 193 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 194 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 195 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 196 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 197 198 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 199 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 200 #define SCU_HW_STRAP_SPI_DIS 0 201 #define SCU_HW_STRAP_SPI_MASTER 1 202 #define SCU_HW_STRAP_SPI_M_S_EN 2 203 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 204 205 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 206 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 207 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 208 #define AST2400_CPU_AHB_RATIO_1_1 0 209 #define AST2400_CPU_AHB_RATIO_2_1 1 210 #define AST2400_CPU_AHB_RATIO_4_1 2 211 #define AST2400_CPU_AHB_RATIO_3_1 3 212 213 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 214 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 215 #define AST2400_CPU_384MHZ 0 216 #define AST2400_CPU_360MHZ 1 217 #define AST2400_CPU_336MHZ 2 218 #define AST2400_CPU_408MHZ 3 219 220 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 221 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 222 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 223 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 224 225 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 226 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 227 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 228 #define VGA_8M_DRAM 0 229 #define VGA_16M_DRAM 1 230 #define VGA_32M_DRAM 2 231 #define VGA_64M_DRAM 3 232 233 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 234 #define AST2400_NOR_BOOT 0 235 #define AST2400_NAND_BOOT 1 236 #define AST2400_SPI_BOOT 2 237 #define AST2400_DIS_BOOT 3 238 239 /* 240 * SCU70 Hardware strapping register definition (for Aspeed AST2500 241 * SoC and higher) 242 * 243 * 31 Enable SPI Flash Strap Auto Fetch Mode 244 * 30 Enable GPIO Strap Mode 245 * 29 Select UART Debug Port 246 * 28 Reserved (1) 247 * 27 Enable fast reset mode for ARM ICE debugger 248 * 26 Enable eSPI flash mode 249 * 25 Enable eSPI mode 250 * 24 Select DDR4 SDRAM 251 * 23 Select 25 MHz reference clock input mode 252 * 22 Enable GPIOE pass-through mode 253 * 21 Enable GPIOD pass-through mode 254 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 255 * 19 Enable ACPI function 256 * 18 Select USBCKI input frequency 257 * 17 Enable BMC 2nd boot watchdog timer 258 * 16 SuperIO configuration address selection 259 * 15 VGA Class Code selection 260 * 14 Select dedicated LPC reset input 261 * 13:12 SPI mode selection 262 * 11:9 AXI/AHB clock frequency ratio selection 263 * 8 Reserved (0) 264 * 7 Define MAC#2 interface 265 * 6 Define MAC#1 interface 266 * 5 Enable dedicated VGA BIOS ROM 267 * 4 Reserved (0) 268 * 3:2 VGA memory size selection 269 * 1 Reserved (1) 270 * 0 Disable CPU boot 271 */ 272 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 273 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 274 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 275 #define UART_DEBUG_UART1 0 276 #define UART_DEBUG_UART5 1 277 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 278 279 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 280 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 281 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 282 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 283 284 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 285 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 286 #define USBCKI_FREQ_24MHZ 0 287 #define USBCKI_FREQ_28MHZ 1 288 289 #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 290 #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 291 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 292 #define AXI_AHB_RATIO_UNDEFINED 0 293 #define AXI_AHB_RATIO_2_1 1 294 #define AXI_AHB_RATIO_3_1 2 295 #define AXI_AHB_RATIO_4_1 3 296 #define AXI_AHB_RATIO_5_1 4 297 #define AXI_AHB_RATIO_6_1 5 298 #define AXI_AHB_RATIO_7_1 6 299 #define AXI_AHB_RATIO_8_1 7 300 301 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 302 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 303 304 #define AST2500_HW_STRAP1_DEFAULTS ( \ 305 SCU_AST2500_HW_STRAP_RESERVED28 | \ 306 SCU_HW_STRAP_2ND_BOOT_WDT | \ 307 SCU_HW_STRAP_VGA_CLASS_CODE | \ 308 SCU_HW_STRAP_LPC_RESET_PIN | \ 309 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 310 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 311 SCU_AST2500_HW_STRAP_RESERVED1) 312 313 #endif /* ASPEED_SCU_H */ 314