1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 #ifndef ASPEED_SCU_H 12 #define ASPEED_SCU_H 13 14 #include "hw/sysbus.h" 15 #include "qom/object.h" 16 17 #define TYPE_ASPEED_SCU "aspeed.scu" 18 OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU) 19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" 20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" 21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" 22 23 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 24 #define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) 25 26 struct AspeedSCUState { 27 /*< private >*/ 28 SysBusDevice parent_obj; 29 30 /*< public >*/ 31 MemoryRegion iomem; 32 33 uint32_t regs[ASPEED_AST2600_SCU_NR_REGS]; 34 uint32_t silicon_rev; 35 uint32_t hw_strap1; 36 uint32_t hw_strap2; 37 uint32_t hw_prot_key; 38 }; 39 40 #define AST2400_A0_SILICON_REV 0x02000303U 41 #define AST2400_A1_SILICON_REV 0x02010303U 42 #define AST2500_A0_SILICON_REV 0x04000303U 43 #define AST2500_A1_SILICON_REV 0x04010303U 44 #define AST2600_A0_SILICON_REV 0x05000303U 45 #define AST2600_A1_SILICON_REV 0x05010303U 46 47 #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) 48 49 extern bool is_supported_silicon_rev(uint32_t silicon_rev); 50 51 52 struct AspeedSCUClass { 53 SysBusDeviceClass parent_class; 54 55 const uint32_t *resets; 56 uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); 57 uint32_t apb_divider; 58 uint32_t nr_regs; 59 const MemoryRegionOps *ops; 60 }; 61 62 #define ASPEED_SCU_PROT_KEY 0x1688A8A8 63 64 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); 65 66 /* 67 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 68 * were added. 69 * 70 * Original header file : 71 * arch/arm/mach-aspeed/include/mach/regs-scu.h 72 * 73 * Copyright (C) 2012-2020 ASPEED Technology Inc. 74 * 75 * This program is free software; you can redistribute it and/or modify 76 * it under the terms of the GNU General Public License version 2 as 77 * published by the Free Software Foundation. 78 * 79 * History : 80 * 1. 2012/12/29 Ryan Chen Create 81 */ 82 83 /* SCU08 Clock Selection Register 84 * 85 * 31 Enable Video Engine clock dynamic slow down 86 * 30:28 Video Engine clock slow down setting 87 * 27 2D Engine GCLK clock source selection 88 * 26 2D Engine GCLK clock throttling enable 89 * 25:23 APB PCLK divider selection 90 * 22:20 LPC Host LHCLK divider selection 91 * 19 LPC Host LHCLK clock generation/output enable control 92 * 18:16 MAC AHB bus clock divider selection 93 * 15 SD/SDIO clock running enable 94 * 14:12 SD/SDIO divider selection 95 * 11 Reserved 96 * 10:8 Video port output clock delay control bit 97 * 7 ARM CPU/AHB clock slow down enable 98 * 6:4 ARM CPU/AHB clock slow down setting 99 * 3:2 ECLK clock source selection 100 * 1 CPU/AHB clock slow down idle timer 101 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) 102 */ 103 #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) 104 105 /* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) 106 * 107 * 18 H-PLL parameter selection 108 * 0: Select H-PLL by strapping resistors 109 * 1: Select H-PLL by the programmed registers (SCU24[17:0]) 110 * 17 Enable H-PLL bypass mode 111 * 16 Turn off H-PLL 112 * 10:5 H-PLL Numerator 113 * 4 H-PLL Output Divider 114 * 3:0 H-PLL Denumerator 115 * 116 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)] 117 */ 118 119 #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) 120 #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) 121 #define SCU_AST2400_H_PLL_OFF (0x1 << 16) 122 123 /* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) 124 * 125 * 21 Enable H-PLL reset 126 * 20 Enable H-PLL bypass mode 127 * 19 Turn off H-PLL 128 * 18:13 H-PLL Post Divider 129 * 12:5 H-PLL Numerator (M) 130 * 4:0 H-PLL Denumerator (N) 131 * 132 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) 133 * 134 * The default frequency is 792Mhz when CLKIN = 24MHz 135 */ 136 137 #define SCU_H_PLL_BYPASS_EN (0x1 << 20) 138 #define SCU_H_PLL_OFF (0x1 << 19) 139 140 /* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) 141 * 142 * 31:29 Software defined strapping registers 143 * 28:27 DRAM size setting (for VGA driver use) 144 * 26:24 DRAM configuration setting 145 * 23 Enable 25 MHz reference clock input 146 * 22 Enable GPIOE pass-through mode 147 * 21 Enable GPIOD pass-through mode 148 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 149 * 19 Disable ACPI function 150 * 23,18 Clock source selection 151 * 17 Enable BMC 2nd boot watchdog timer 152 * 16 SuperIO configuration address selection 153 * 15 VGA Class Code selection 154 * 14 Enable LPC dedicated reset pin function 155 * 13:12 SPI mode selection 156 * 11:10 CPU/AHB clock frequency ratio selection 157 * 9:8 H-PLL default clock frequency selection 158 * 7 Define MAC#2 interface 159 * 6 Define MAC#1 interface 160 * 5 Enable VGA BIOS ROM 161 * 4 Boot flash memory extended option 162 * 3:2 VGA memory size selection 163 * 1:0 BMC CPU boot code selection 164 */ 165 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 166 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 167 168 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 169 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 170 #define DRAM_SIZE_64MB 0 171 #define DRAM_SIZE_128MB 1 172 #define DRAM_SIZE_256MB 2 173 #define DRAM_SIZE_512MB 3 174 175 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 176 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 177 178 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 179 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 180 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 181 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 182 183 /* bit 23, 18 [1,0] */ 184 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 185 | (((x) & 0x1) << 18)) 186 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 187 | (((x) >> 18) & 0x1)) 188 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 189 #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) 190 #define AST2400_CLK_24M_IN 0 191 #define AST2400_CLK_48M_IN 1 192 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 193 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 194 195 #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) 196 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 197 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 198 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 199 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 200 201 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 202 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 203 #define SCU_HW_STRAP_SPI_DIS 0 204 #define SCU_HW_STRAP_SPI_MASTER 1 205 #define SCU_HW_STRAP_SPI_M_S_EN 2 206 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 207 208 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 209 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 210 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 211 #define AST2400_CPU_AHB_RATIO_1_1 0 212 #define AST2400_CPU_AHB_RATIO_2_1 1 213 #define AST2400_CPU_AHB_RATIO_4_1 2 214 #define AST2400_CPU_AHB_RATIO_3_1 3 215 216 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 217 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 218 #define AST2400_CPU_384MHZ 0 219 #define AST2400_CPU_360MHZ 1 220 #define AST2400_CPU_336MHZ 2 221 #define AST2400_CPU_408MHZ 3 222 223 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 224 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 225 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 226 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 227 228 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 229 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 230 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 231 #define VGA_8M_DRAM 0 232 #define VGA_16M_DRAM 1 233 #define VGA_32M_DRAM 2 234 #define VGA_64M_DRAM 3 235 236 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 237 #define AST2400_NOR_BOOT 0 238 #define AST2400_NAND_BOOT 1 239 #define AST2400_SPI_BOOT 2 240 #define AST2400_DIS_BOOT 3 241 242 /* 243 * SCU70 Hardware strapping register definition (for Aspeed AST2500 244 * SoC and higher) 245 * 246 * 31 Enable SPI Flash Strap Auto Fetch Mode 247 * 30 Enable GPIO Strap Mode 248 * 29 Select UART Debug Port 249 * 28 Reserved (1) 250 * 27 Enable fast reset mode for ARM ICE debugger 251 * 26 Enable eSPI flash mode 252 * 25 Enable eSPI mode 253 * 24 Select DDR4 SDRAM 254 * 23 Select 25 MHz reference clock input mode 255 * 22 Enable GPIOE pass-through mode 256 * 21 Enable GPIOD pass-through mode 257 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 258 * 19 Enable ACPI function 259 * 18 Select USBCKI input frequency 260 * 17 Enable BMC 2nd boot watchdog timer 261 * 16 SuperIO configuration address selection 262 * 15 VGA Class Code selection 263 * 14 Select dedicated LPC reset input 264 * 13:12 SPI mode selection 265 * 11:9 AXI/AHB clock frequency ratio selection 266 * 8 Reserved (0) 267 * 7 Define MAC#2 interface 268 * 6 Define MAC#1 interface 269 * 5 Enable dedicated VGA BIOS ROM 270 * 4 Reserved (0) 271 * 3:2 VGA memory size selection 272 * 1 Reserved (1) 273 * 0 Disable CPU boot 274 */ 275 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 276 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 277 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 278 #define UART_DEBUG_UART1 0 279 #define UART_DEBUG_UART5 1 280 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 281 282 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 283 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 284 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 285 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 286 #define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23) 287 288 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 289 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 290 #define USBCKI_FREQ_24MHZ 0 291 #define USBCKI_FREQ_28MHZ 1 292 293 #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 294 #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 295 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 296 #define AXI_AHB_RATIO_UNDEFINED 0 297 #define AXI_AHB_RATIO_2_1 1 298 #define AXI_AHB_RATIO_3_1 2 299 #define AXI_AHB_RATIO_4_1 3 300 #define AXI_AHB_RATIO_5_1 4 301 #define AXI_AHB_RATIO_6_1 5 302 #define AXI_AHB_RATIO_7_1 6 303 #define AXI_AHB_RATIO_8_1 7 304 305 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 306 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 307 308 #define AST2500_HW_STRAP1_DEFAULTS ( \ 309 SCU_AST2500_HW_STRAP_RESERVED28 | \ 310 SCU_HW_STRAP_2ND_BOOT_WDT | \ 311 SCU_HW_STRAP_VGA_CLASS_CODE | \ 312 SCU_HW_STRAP_LPC_RESET_PIN | \ 313 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 314 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 315 SCU_AST2500_HW_STRAP_RESERVED1) 316 317 #endif /* ASPEED_SCU_H */ 318