1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 #ifndef ASPEED_SCU_H 12 #define ASPEED_SCU_H 13 14 #include "hw/sysbus.h" 15 16 #define TYPE_ASPEED_SCU "aspeed.scu" 17 #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) 18 19 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 20 21 typedef struct AspeedSCUState { 22 /*< private >*/ 23 SysBusDevice parent_obj; 24 25 /*< public >*/ 26 MemoryRegion iomem; 27 28 uint32_t regs[ASPEED_SCU_NR_REGS]; 29 uint32_t silicon_rev; 30 uint32_t hw_strap1; 31 uint32_t hw_strap2; 32 } AspeedSCUState; 33 34 #define AST2400_A0_SILICON_REV 0x02000303U 35 #define AST2500_A0_SILICON_REV 0x04000303U 36 #define AST2500_A1_SILICON_REV 0x04010303U 37 38 extern bool is_supported_silicon_rev(uint32_t silicon_rev); 39 40 /* 41 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 42 * were added. 43 * 44 * Original header file : 45 * arch/arm/mach-aspeed/include/mach/regs-scu.h 46 * 47 * Copyright (C) 2012-2020 ASPEED Technology Inc. 48 * 49 * This program is free software; you can redistribute it and/or modify 50 * it under the terms of the GNU General Public License version 2 as 51 * published by the Free Software Foundation. 52 * 53 * History : 54 * 1. 2012/12/29 Ryan Chen Create 55 */ 56 57 /* Hardware Strapping Register definition (for Aspeed AST2400 SOC) 58 * 59 * 31:29 Software defined strapping registers 60 * 28:27 DRAM size setting (for VGA driver use) 61 * 26:24 DRAM configuration setting 62 * 23 Enable 25 MHz reference clock input 63 * 22 Enable GPIOE pass-through mode 64 * 21 Enable GPIOD pass-through mode 65 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 66 * 19 Disable ACPI function 67 * 23,18 Clock source selection 68 * 17 Enable BMC 2nd boot watchdog timer 69 * 16 SuperIO configuration address selection 70 * 15 VGA Class Code selection 71 * 14 Enable LPC dedicated reset pin function 72 * 13:12 SPI mode selection 73 * 11:10 CPU/AHB clock frequency ratio selection 74 * 9:8 H-PLL default clock frequency selection 75 * 7 Define MAC#2 interface 76 * 6 Define MAC#1 interface 77 * 5 Enable VGA BIOS ROM 78 * 4 Boot flash memory extended option 79 * 3:2 VGA memory size selection 80 * 1:0 BMC CPU boot code selection 81 */ 82 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 83 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 84 85 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 86 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 87 #define DRAM_SIZE_64MB 0 88 #define DRAM_SIZE_128MB 1 89 #define DRAM_SIZE_256MB 2 90 #define DRAM_SIZE_512MB 3 91 92 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 93 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 94 95 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 96 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 97 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 98 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 99 100 /* bit 23, 18 [1,0] */ 101 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 102 | (((x) & 0x1) << 18)) 103 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 104 | (((x) >> 18) & 0x1)) 105 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 106 #define AST2400_CLK_25M_IN (0x1 << 23) 107 #define AST2400_CLK_24M_IN 0 108 #define AST2400_CLK_48M_IN 1 109 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 110 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 111 112 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 113 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 114 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 115 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 116 117 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 118 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 119 #define SCU_HW_STRAP_SPI_DIS 0 120 #define SCU_HW_STRAP_SPI_MASTER 1 121 #define SCU_HW_STRAP_SPI_M_S_EN 2 122 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 123 124 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 125 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 126 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 127 #define AST2400_CPU_AHB_RATIO_1_1 0 128 #define AST2400_CPU_AHB_RATIO_2_1 1 129 #define AST2400_CPU_AHB_RATIO_4_1 2 130 #define AST2400_CPU_AHB_RATIO_3_1 3 131 132 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 133 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 134 #define AST2400_CPU_384MHZ 0 135 #define AST2400_CPU_360MHZ 1 136 #define AST2400_CPU_336MHZ 2 137 #define AST2400_CPU_408MHZ 3 138 139 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 140 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 141 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 142 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 143 144 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 145 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 146 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 147 #define VGA_8M_DRAM 0 148 #define VGA_16M_DRAM 1 149 #define VGA_32M_DRAM 2 150 #define VGA_64M_DRAM 3 151 152 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 153 #define AST2400_NOR_BOOT 0 154 #define AST2400_NAND_BOOT 1 155 #define AST2400_SPI_BOOT 2 156 #define AST2400_DIS_BOOT 3 157 158 /* 159 * Hardware strapping register definition (for Aspeed AST2500 SoC and 160 * higher) 161 * 162 * 31 Enable SPI Flash Strap Auto Fetch Mode 163 * 30 Enable GPIO Strap Mode 164 * 29 Select UART Debug Port 165 * 28 Reserved (1) 166 * 27 Enable fast reset mode for ARM ICE debugger 167 * 26 Enable eSPI flash mode 168 * 25 Enable eSPI mode 169 * 24 Select DDR4 SDRAM 170 * 23 Select 25 MHz reference clock input mode 171 * 22 Enable GPIOE pass-through mode 172 * 21 Enable GPIOD pass-through mode 173 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 174 * 19 Enable ACPI function 175 * 18 Select USBCKI input frequency 176 * 17 Enable BMC 2nd boot watchdog timer 177 * 16 SuperIO configuration address selection 178 * 15 VGA Class Code selection 179 * 14 Select dedicated LPC reset input 180 * 13:12 SPI mode selection 181 * 11:9 AXI/AHB clock frequency ratio selection 182 * 8 Reserved (0) 183 * 7 Define MAC#2 interface 184 * 6 Define MAC#1 interface 185 * 5 Enable dedicated VGA BIOS ROM 186 * 4 Reserved (0) 187 * 3:2 VGA memory size selection 188 * 1 Reserved (1) 189 * 0 Disable CPU boot 190 */ 191 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 192 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 193 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 194 #define UART_DEBUG_UART1 0 195 #define UART_DEBUG_UART5 1 196 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 197 198 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 199 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 200 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 201 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 202 203 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 204 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 205 #define USBCKI_FREQ_24MHZ 0 206 #define USBCKI_FREQ_28MHZ 1 207 208 #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 209 #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 210 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 211 #define AXI_AHB_RATIO_UNDEFINED 0 212 #define AXI_AHB_RATIO_2_1 1 213 #define AXI_AHB_RATIO_3_1 2 214 #define AXI_AHB_RATIO_4_1 3 215 #define AXI_AHB_RATIO_5_1 4 216 #define AXI_AHB_RATIO_6_1 5 217 #define AXI_AHB_RATIO_7_1 6 218 #define AXI_AHB_RATIO_8_1 7 219 220 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 221 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 222 223 #define AST2500_HW_STRAP1_DEFAULTS ( \ 224 SCU_AST2500_HW_STRAP_RESERVED28 | \ 225 SCU_HW_STRAP_2ND_BOOT_WDT | \ 226 SCU_HW_STRAP_VGA_CLASS_CODE | \ 227 SCU_HW_STRAP_LPC_RESET_PIN | \ 228 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 229 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 230 SCU_AST2500_HW_STRAP_RESERVED1) 231 232 #endif /* ASPEED_SCU_H */ 233