1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 #ifndef ASPEED_SCU_H 12 #define ASPEED_SCU_H 13 14 #include "hw/sysbus.h" 15 16 #define TYPE_ASPEED_SCU "aspeed.scu" 17 #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) 18 19 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 20 21 typedef struct AspeedSCUState { 22 /*< private >*/ 23 SysBusDevice parent_obj; 24 25 /*< public >*/ 26 MemoryRegion iomem; 27 28 uint32_t regs[ASPEED_SCU_NR_REGS]; 29 uint32_t silicon_rev; 30 uint32_t hw_strap1; 31 uint32_t hw_strap2; 32 uint32_t hw_prot_key; 33 } AspeedSCUState; 34 35 #define AST2400_A0_SILICON_REV 0x02000303U 36 #define AST2400_A1_SILICON_REV 0x02010303U 37 #define AST2500_A0_SILICON_REV 0x04000303U 38 #define AST2500_A1_SILICON_REV 0x04010303U 39 40 extern bool is_supported_silicon_rev(uint32_t silicon_rev); 41 42 #define ASPEED_SCU_PROT_KEY 0x1688A8A8 43 44 /* 45 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 46 * were added. 47 * 48 * Original header file : 49 * arch/arm/mach-aspeed/include/mach/regs-scu.h 50 * 51 * Copyright (C) 2012-2020 ASPEED Technology Inc. 52 * 53 * This program is free software; you can redistribute it and/or modify 54 * it under the terms of the GNU General Public License version 2 as 55 * published by the Free Software Foundation. 56 * 57 * History : 58 * 1. 2012/12/29 Ryan Chen Create 59 */ 60 61 /* Hardware Strapping Register definition (for Aspeed AST2400 SOC) 62 * 63 * 31:29 Software defined strapping registers 64 * 28:27 DRAM size setting (for VGA driver use) 65 * 26:24 DRAM configuration setting 66 * 23 Enable 25 MHz reference clock input 67 * 22 Enable GPIOE pass-through mode 68 * 21 Enable GPIOD pass-through mode 69 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 70 * 19 Disable ACPI function 71 * 23,18 Clock source selection 72 * 17 Enable BMC 2nd boot watchdog timer 73 * 16 SuperIO configuration address selection 74 * 15 VGA Class Code selection 75 * 14 Enable LPC dedicated reset pin function 76 * 13:12 SPI mode selection 77 * 11:10 CPU/AHB clock frequency ratio selection 78 * 9:8 H-PLL default clock frequency selection 79 * 7 Define MAC#2 interface 80 * 6 Define MAC#1 interface 81 * 5 Enable VGA BIOS ROM 82 * 4 Boot flash memory extended option 83 * 3:2 VGA memory size selection 84 * 1:0 BMC CPU boot code selection 85 */ 86 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 87 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 88 89 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 90 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 91 #define DRAM_SIZE_64MB 0 92 #define DRAM_SIZE_128MB 1 93 #define DRAM_SIZE_256MB 2 94 #define DRAM_SIZE_512MB 3 95 96 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 97 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 98 99 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 100 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 101 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 102 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 103 104 /* bit 23, 18 [1,0] */ 105 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 106 | (((x) & 0x1) << 18)) 107 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 108 | (((x) >> 18) & 0x1)) 109 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 110 #define AST2400_CLK_25M_IN (0x1 << 23) 111 #define AST2400_CLK_24M_IN 0 112 #define AST2400_CLK_48M_IN 1 113 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 114 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 115 116 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 117 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 118 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 119 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 120 121 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 122 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 123 #define SCU_HW_STRAP_SPI_DIS 0 124 #define SCU_HW_STRAP_SPI_MASTER 1 125 #define SCU_HW_STRAP_SPI_M_S_EN 2 126 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 127 128 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 129 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 130 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 131 #define AST2400_CPU_AHB_RATIO_1_1 0 132 #define AST2400_CPU_AHB_RATIO_2_1 1 133 #define AST2400_CPU_AHB_RATIO_4_1 2 134 #define AST2400_CPU_AHB_RATIO_3_1 3 135 136 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 137 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 138 #define AST2400_CPU_384MHZ 0 139 #define AST2400_CPU_360MHZ 1 140 #define AST2400_CPU_336MHZ 2 141 #define AST2400_CPU_408MHZ 3 142 143 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 144 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 145 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 146 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 147 148 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 149 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 150 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 151 #define VGA_8M_DRAM 0 152 #define VGA_16M_DRAM 1 153 #define VGA_32M_DRAM 2 154 #define VGA_64M_DRAM 3 155 156 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 157 #define AST2400_NOR_BOOT 0 158 #define AST2400_NAND_BOOT 1 159 #define AST2400_SPI_BOOT 2 160 #define AST2400_DIS_BOOT 3 161 162 /* 163 * Hardware strapping register definition (for Aspeed AST2500 SoC and 164 * higher) 165 * 166 * 31 Enable SPI Flash Strap Auto Fetch Mode 167 * 30 Enable GPIO Strap Mode 168 * 29 Select UART Debug Port 169 * 28 Reserved (1) 170 * 27 Enable fast reset mode for ARM ICE debugger 171 * 26 Enable eSPI flash mode 172 * 25 Enable eSPI mode 173 * 24 Select DDR4 SDRAM 174 * 23 Select 25 MHz reference clock input mode 175 * 22 Enable GPIOE pass-through mode 176 * 21 Enable GPIOD pass-through mode 177 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 178 * 19 Enable ACPI function 179 * 18 Select USBCKI input frequency 180 * 17 Enable BMC 2nd boot watchdog timer 181 * 16 SuperIO configuration address selection 182 * 15 VGA Class Code selection 183 * 14 Select dedicated LPC reset input 184 * 13:12 SPI mode selection 185 * 11:9 AXI/AHB clock frequency ratio selection 186 * 8 Reserved (0) 187 * 7 Define MAC#2 interface 188 * 6 Define MAC#1 interface 189 * 5 Enable dedicated VGA BIOS ROM 190 * 4 Reserved (0) 191 * 3:2 VGA memory size selection 192 * 1 Reserved (1) 193 * 0 Disable CPU boot 194 */ 195 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 196 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 197 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 198 #define UART_DEBUG_UART1 0 199 #define UART_DEBUG_UART5 1 200 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 201 202 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 203 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 204 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 205 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 206 207 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 208 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 209 #define USBCKI_FREQ_24MHZ 0 210 #define USBCKI_FREQ_28MHZ 1 211 212 #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 213 #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 214 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 215 #define AXI_AHB_RATIO_UNDEFINED 0 216 #define AXI_AHB_RATIO_2_1 1 217 #define AXI_AHB_RATIO_3_1 2 218 #define AXI_AHB_RATIO_4_1 3 219 #define AXI_AHB_RATIO_5_1 4 220 #define AXI_AHB_RATIO_6_1 5 221 #define AXI_AHB_RATIO_7_1 6 222 #define AXI_AHB_RATIO_8_1 7 223 224 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 225 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 226 227 #define AST2500_HW_STRAP1_DEFAULTS ( \ 228 SCU_AST2500_HW_STRAP_RESERVED28 | \ 229 SCU_HW_STRAP_2ND_BOOT_WDT | \ 230 SCU_HW_STRAP_VGA_CLASS_CODE | \ 231 SCU_HW_STRAP_LPC_RESET_PIN | \ 232 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 233 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 234 SCU_AST2500_HW_STRAP_RESERVED1) 235 236 #endif /* ASPEED_SCU_H */ 237