1 /* 2 * ASPEED System Control Unit 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 #ifndef ASPEED_SCU_H 12 #define ASPEED_SCU_H 13 14 #include "hw/sysbus.h" 15 #include "qom/object.h" 16 17 #define TYPE_ASPEED_SCU "aspeed.scu" 18 OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU) 19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" 20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" 21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" 22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700" 23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700" 24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030" 25 26 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 27 #define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) 28 #define ASPEED_AST2700_SCU_NR_REGS (0xE20 >> 2) 29 30 struct AspeedSCUState { 31 /*< private >*/ 32 SysBusDevice parent_obj; 33 34 /*< public >*/ 35 MemoryRegion iomem; 36 37 uint32_t regs[ASPEED_AST2700_SCU_NR_REGS]; 38 uint32_t silicon_rev; 39 uint32_t hw_strap1; 40 uint32_t hw_strap2; 41 uint32_t hw_prot_key; 42 }; 43 44 #define AST2400_A0_SILICON_REV 0x02000303U 45 #define AST2400_A1_SILICON_REV 0x02010303U 46 #define AST2500_A0_SILICON_REV 0x04000303U 47 #define AST2500_A1_SILICON_REV 0x04010303U 48 #define AST2600_A0_SILICON_REV 0x05000303U 49 #define AST2600_A1_SILICON_REV 0x05010303U 50 #define AST2600_A2_SILICON_REV 0x05020303U 51 #define AST2600_A3_SILICON_REV 0x05030303U 52 #define AST1030_A0_SILICON_REV 0x80000000U 53 #define AST1030_A1_SILICON_REV 0x80010000U 54 #define AST2700_A0_SILICON_REV 0x06000103U 55 #define AST2720_A0_SILICON_REV 0x06000203U 56 #define AST2750_A0_SILICON_REV 0x06000003U 57 58 #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) 59 60 bool is_supported_silicon_rev(uint32_t silicon_rev); 61 62 63 struct AspeedSCUClass { 64 SysBusDeviceClass parent_class; 65 66 const uint32_t *resets; 67 uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); 68 uint32_t (*get_apb)(AspeedSCUState *s); 69 uint32_t apb_divider; 70 uint32_t nr_regs; 71 bool clkin_25Mhz; 72 const MemoryRegionOps *ops; 73 }; 74 75 #define ASPEED_SCU_PROT_KEY 0x1688A8A8 76 77 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); 78 79 /* 80 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 81 * were added. 82 * 83 * Original header file : 84 * arch/arm/mach-aspeed/include/mach/regs-scu.h 85 * 86 * Copyright (C) 2012-2020 ASPEED Technology Inc. 87 * 88 * This program is free software; you can redistribute it and/or modify 89 * it under the terms of the GNU General Public License version 2 as 90 * published by the Free Software Foundation. 91 * 92 * History : 93 * 1. 2012/12/29 Ryan Chen Create 94 */ 95 96 /* 97 * SCU08 Clock Selection Register 98 * 99 * 31 Enable Video Engine clock dynamic slow down 100 * 30:28 Video Engine clock slow down setting 101 * 27 2D Engine GCLK clock source selection 102 * 26 2D Engine GCLK clock throttling enable 103 * 25:23 APB PCLK divider selection 104 * 22:20 LPC Host LHCLK divider selection 105 * 19 LPC Host LHCLK clock generation/output enable control 106 * 18:16 MAC AHB bus clock divider selection 107 * 15 SD/SDIO clock running enable 108 * 14:12 SD/SDIO divider selection 109 * 11 Reserved 110 * 10:8 Video port output clock delay control bit 111 * 7 ARM CPU/AHB clock slow down enable 112 * 6:4 ARM CPU/AHB clock slow down setting 113 * 3:2 ECLK clock source selection 114 * 1 CPU/AHB clock slow down idle timer 115 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) 116 */ 117 #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) 118 119 /* 120 * SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) 121 * 122 * 18 H-PLL parameter selection 123 * 0: Select H-PLL by strapping resistors 124 * 1: Select H-PLL by the programmed registers (SCU24[17:0]) 125 * 17 Enable H-PLL bypass mode 126 * 16 Turn off H-PLL 127 * 10:5 H-PLL Numerator 128 * 4 H-PLL Output Divider 129 * 3:0 H-PLL Denumerator 130 * 131 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)] 132 */ 133 134 #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) 135 #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) 136 #define SCU_AST2400_H_PLL_OFF (0x1 << 16) 137 138 /* 139 * SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) 140 * 141 * 21 Enable H-PLL reset 142 * 20 Enable H-PLL bypass mode 143 * 19 Turn off H-PLL 144 * 18:13 H-PLL Post Divider 145 * 12:5 H-PLL Numerator (M) 146 * 4:0 H-PLL Denumerator (N) 147 * 148 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) 149 * 150 * The default frequency is 792Mhz when CLKIN = 24MHz 151 */ 152 153 #define SCU_H_PLL_BYPASS_EN (0x1 << 20) 154 #define SCU_H_PLL_OFF (0x1 << 19) 155 156 /* 157 * SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) 158 * 159 * 31:29 Software defined strapping registers 160 * 28:27 DRAM size setting (for VGA driver use) 161 * 26:24 DRAM configuration setting 162 * 23 Enable 25 MHz reference clock input 163 * 22 Enable GPIOE pass-through mode 164 * 21 Enable GPIOD pass-through mode 165 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 166 * 19 Disable ACPI function 167 * 23,18 Clock source selection 168 * 17 Enable BMC 2nd boot watchdog timer 169 * 16 SuperIO configuration address selection 170 * 15 VGA Class Code selection 171 * 14 Enable LPC dedicated reset pin function 172 * 13:12 SPI mode selection 173 * 11:10 CPU/AHB clock frequency ratio selection 174 * 9:8 H-PLL default clock frequency selection 175 * 7 Define MAC#2 interface 176 * 6 Define MAC#1 interface 177 * 5 Enable VGA BIOS ROM 178 * 4 Boot flash memory extended option 179 * 3:2 VGA memory size selection 180 * 1:0 BMC CPU boot code selection 181 */ 182 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 183 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 184 185 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 186 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 187 #define DRAM_SIZE_64MB 0 188 #define DRAM_SIZE_128MB 1 189 #define DRAM_SIZE_256MB 2 190 #define DRAM_SIZE_512MB 3 191 192 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 193 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 194 195 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 196 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 197 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 198 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 199 200 /* bit 23, 18 [1,0] */ 201 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 202 | (((x) & 0x1) << 18)) 203 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 204 | (((x) >> 18) & 0x1)) 205 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 206 #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) 207 #define AST2400_CLK_24M_IN 0 208 #define AST2400_CLK_48M_IN 1 209 #define AST2400_CLK_25M_IN_24M_USB_CKI 2 210 #define AST2400_CLK_25M_IN_48M_USB_CKI 3 211 212 #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) 213 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 214 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 215 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 216 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 217 218 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 219 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 220 #define SCU_HW_STRAP_SPI_DIS 0 221 #define SCU_HW_STRAP_SPI_MASTER 1 222 #define SCU_HW_STRAP_SPI_M_S_EN 2 223 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 224 225 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 226 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 227 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 228 #define AST2400_CPU_AHB_RATIO_1_1 0 229 #define AST2400_CPU_AHB_RATIO_2_1 1 230 #define AST2400_CPU_AHB_RATIO_4_1 2 231 #define AST2400_CPU_AHB_RATIO_3_1 3 232 233 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 234 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 235 #define AST2400_CPU_384MHZ 0 236 #define AST2400_CPU_360MHZ 1 237 #define AST2400_CPU_336MHZ 2 238 #define AST2400_CPU_408MHZ 3 239 240 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 241 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 242 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 243 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 244 245 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 246 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 247 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 248 #define VGA_8M_DRAM 0 249 #define VGA_16M_DRAM 1 250 #define VGA_32M_DRAM 2 251 #define VGA_64M_DRAM 3 252 253 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 254 #define AST2400_NOR_BOOT 0 255 #define AST2400_NAND_BOOT 1 256 #define AST2400_SPI_BOOT 2 257 #define AST2400_DIS_BOOT 3 258 259 /* 260 * SCU70 Hardware strapping register definition (for Aspeed AST2500 261 * SoC and higher) 262 * 263 * 31 Enable SPI Flash Strap Auto Fetch Mode 264 * 30 Enable GPIO Strap Mode 265 * 29 Select UART Debug Port 266 * 28 Reserved (1) 267 * 27 Enable fast reset mode for ARM ICE debugger 268 * 26 Enable eSPI flash mode 269 * 25 Enable eSPI mode 270 * 24 Select DDR4 SDRAM 271 * 23 Select 25 MHz reference clock input mode 272 * 22 Enable GPIOE pass-through mode 273 * 21 Enable GPIOD pass-through mode 274 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 275 * 19 Enable ACPI function 276 * 18 Select USBCKI input frequency 277 * 17 Enable BMC 2nd boot watchdog timer 278 * 16 SuperIO configuration address selection 279 * 15 VGA Class Code selection 280 * 14 Select dedicated LPC reset input 281 * 13:12 SPI mode selection 282 * 11:9 AXI/AHB clock frequency ratio selection 283 * 8 Reserved (0) 284 * 7 Define MAC#2 interface 285 * 6 Define MAC#1 interface 286 * 5 Enable dedicated VGA BIOS ROM 287 * 4 Reserved (0) 288 * 3:2 VGA memory size selection 289 * 1 Reserved (1) 290 * 0 Disable CPU boot 291 */ 292 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 293 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 294 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 295 #define UART_DEBUG_UART1 0 296 #define UART_DEBUG_UART5 1 297 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 298 299 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 300 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 301 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 302 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 303 #define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23) 304 305 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 306 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 307 #define USBCKI_FREQ_24MHZ 0 308 #define USBCKI_FREQ_28MHZ 1 309 310 #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 311 #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 312 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 313 #define AXI_AHB_RATIO_UNDEFINED 0 314 #define AXI_AHB_RATIO_2_1 1 315 #define AXI_AHB_RATIO_3_1 2 316 #define AXI_AHB_RATIO_4_1 3 317 #define AXI_AHB_RATIO_5_1 4 318 #define AXI_AHB_RATIO_6_1 5 319 #define AXI_AHB_RATIO_7_1 6 320 #define AXI_AHB_RATIO_8_1 7 321 322 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 323 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 324 325 #define AST2500_HW_STRAP1_DEFAULTS ( \ 326 SCU_AST2500_HW_STRAP_RESERVED28 | \ 327 SCU_HW_STRAP_2ND_BOOT_WDT | \ 328 SCU_HW_STRAP_VGA_CLASS_CODE | \ 329 SCU_HW_STRAP_LPC_RESET_PIN | \ 330 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 331 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 332 SCU_AST2500_HW_STRAP_RESERVED1) 333 334 /* 335 * SCU200 H-PLL Parameter Register (for Aspeed AST2600 SOC) 336 * 337 * 28:26 H-PLL Parameters 338 * 25 Enable H-PLL reset 339 * 24 Enable H-PLL bypass mode 340 * 23 Turn off H-PLL 341 * 22:19 H-PLL Post Divider (P) 342 * 18:13 H-PLL Numerator (M) 343 * 12:0 H-PLL Denumerator (N) 344 * 345 * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1) 346 * 347 * The default frequency is 1200Mhz when CLKIN = 25MHz 348 */ 349 #define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24) 350 #define SCU_AST2600_H_PLL_OFF (0x1 << 23) 351 352 /* 353 * SCU310 Clock Selection Register Set 4 (for Aspeed AST1030 SOC) 354 * 355 * 31 I3C Clock Source selection 356 * 30:28 I3C clock divider selection 357 * 26:24 MAC AHB clock divider selection 358 * 22:20 RGMII 125MHz clock divider ration 359 * 19:16 RGMII 50MHz clock divider ration 360 * 15 LHCLK clock generation/output enable control 361 * 14:12 LHCLK divider selection 362 * 11:8 APB Bus PCLK divider selection 363 * 7 Select PECI clock source 364 * 6 Select UART debug port clock source 365 * 5 Select UART6 clock source 366 * 4 Select UART5 clock source 367 * 3 Select UART4 clock source 368 * 2 Select UART3 clock source 369 * 1 Select UART2 clock source 370 * 0 Select UART1 clock source 371 */ 372 #define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf) 373 374 /* 375 * SCU280 Clock Selection 1 Register (for Aspeed AST2700 SCUIO) 376 * 377 * 31:29 MHCLK_DIV 378 * 28 Reserved 379 * 27:25 RGMIICLK_DIV 380 * 24 Reserved 381 * 23:21 RMIICLK_DIV 382 * 20:18 PCLK_DIV 383 * 17:14 SDCLK_DIV 384 * 13 SDCLK_SEL 385 * 12 UART13CLK_SEL 386 * 11 UART12CLK_SEL 387 * 10 UART11CLK_SEL 388 * 9 UART10CLK_SEL 389 * 8 UART9CLK_SEL 390 * 7 UART8CLK_SEL 391 * 6 UART7CLK_SEL 392 * 5 UART6CLK_SEL 393 * 4 UARTDBCLK_SEL 394 * 3 UART4CLK_SEL 395 * 2 UART3CLK_SEL 396 * 1 UART2CLK_SEL 397 * 0 UART1CLK_SEL 398 */ 399 #define SCUIO_AST2700_CLK_GET_PCLK_DIV(x) (((x) >> 18) & 0x7) 400 401 #endif /* ASPEED_SCU_H */ 402