11c8a2388SAndrew Jeffery /* 21c8a2388SAndrew Jeffery * ASPEED System Control Unit 31c8a2388SAndrew Jeffery * 41c8a2388SAndrew Jeffery * Andrew Jeffery <andrew@aj.id.au> 51c8a2388SAndrew Jeffery * 61c8a2388SAndrew Jeffery * Copyright 2016 IBM Corp. 71c8a2388SAndrew Jeffery * 81c8a2388SAndrew Jeffery * This code is licensed under the GPL version 2 or later. See 91c8a2388SAndrew Jeffery * the COPYING file in the top-level directory. 101c8a2388SAndrew Jeffery */ 111c8a2388SAndrew Jeffery #ifndef ASPEED_SCU_H 121c8a2388SAndrew Jeffery #define ASPEED_SCU_H 131c8a2388SAndrew Jeffery 141c8a2388SAndrew Jeffery #include "hw/sysbus.h" 15db1015e9SEduardo Habkost #include "qom/object.h" 161c8a2388SAndrew Jeffery 171c8a2388SAndrew Jeffery #define TYPE_ASPEED_SCU "aspeed.scu" 18a489d195SEduardo Habkost OBJECT_DECLARE_TYPE(AspeedSCUState, AspeedSCUClass, ASPEED_SCU) 199a937f6cSCédric Le Goater #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" 209a937f6cSCédric Le Goater #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" 21e09cf363SJoel Stanley #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600" 22*fa541a60SSteven Lee #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030" 231c8a2388SAndrew Jeffery 241c8a2388SAndrew Jeffery #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 25e09cf363SJoel Stanley #define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2) 261c8a2388SAndrew Jeffery 27db1015e9SEduardo Habkost struct AspeedSCUState { 281c8a2388SAndrew Jeffery /*< private >*/ 291c8a2388SAndrew Jeffery SysBusDevice parent_obj; 301c8a2388SAndrew Jeffery 311c8a2388SAndrew Jeffery /*< public >*/ 321c8a2388SAndrew Jeffery MemoryRegion iomem; 331c8a2388SAndrew Jeffery 34e09cf363SJoel Stanley uint32_t regs[ASPEED_AST2600_SCU_NR_REGS]; 351c8a2388SAndrew Jeffery uint32_t silicon_rev; 361c8a2388SAndrew Jeffery uint32_t hw_strap1; 371c8a2388SAndrew Jeffery uint32_t hw_strap2; 38b6e70d1dSJoel Stanley uint32_t hw_prot_key; 39db1015e9SEduardo Habkost }; 401c8a2388SAndrew Jeffery 4179a9f323SCédric Le Goater #define AST2400_A0_SILICON_REV 0x02000303U 426efbac90SCédric Le Goater #define AST2400_A1_SILICON_REV 0x02010303U 4379a9f323SCédric Le Goater #define AST2500_A0_SILICON_REV 0x04000303U 44365aff1eSCédric Le Goater #define AST2500_A1_SILICON_REV 0x04010303U 45e09cf363SJoel Stanley #define AST2600_A0_SILICON_REV 0x05000303U 467582591aSJoel Stanley #define AST2600_A1_SILICON_REV 0x05010303U 47c5811bb3SJoel Stanley #define AST2600_A2_SILICON_REV 0x05020303U 48c5811bb3SJoel Stanley #define AST2600_A3_SILICON_REV 0x05030303U 49*fa541a60SSteven Lee #define AST1030_A0_SILICON_REV 0x80000000U 50*fa541a60SSteven Lee #define AST1030_A1_SILICON_REV 0x80010000U 5179a9f323SCédric Le Goater 52333b9c8aSAndrew Jeffery #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) 53333b9c8aSAndrew Jeffery 5479a9f323SCédric Le Goater extern bool is_supported_silicon_rev(uint32_t silicon_rev); 5579a9f323SCédric Le Goater 569a937f6cSCédric Le Goater 57db1015e9SEduardo Habkost struct AspeedSCUClass { 589a937f6cSCédric Le Goater SysBusDeviceClass parent_class; 599a937f6cSCédric Le Goater 609a937f6cSCédric Le Goater const uint32_t *resets; 61a8f07376SCédric Le Goater uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); 62dd7f19a9SSteven Lee uint32_t (*get_apb)(AspeedSCUState *s); 639a937f6cSCédric Le Goater uint32_t apb_divider; 64e09cf363SJoel Stanley uint32_t nr_regs; 65bad23bb6SSteven Lee bool clkin_25Mhz; 66e09cf363SJoel Stanley const MemoryRegionOps *ops; 67db1015e9SEduardo Habkost }; 689a937f6cSCédric Le Goater 69b6e70d1dSJoel Stanley #define ASPEED_SCU_PROT_KEY 0x1688A8A8 70b6e70d1dSJoel Stanley 71a8f07376SCédric Le Goater uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); 72a8f07376SCédric Le Goater 738da33ef7SCédric Le Goater /* 748da33ef7SCédric Le Goater * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 758da33ef7SCédric Le Goater * were added. 768da33ef7SCédric Le Goater * 778da33ef7SCédric Le Goater * Original header file : 788da33ef7SCédric Le Goater * arch/arm/mach-aspeed/include/mach/regs-scu.h 798da33ef7SCédric Le Goater * 808da33ef7SCédric Le Goater * Copyright (C) 2012-2020 ASPEED Technology Inc. 818da33ef7SCédric Le Goater * 828da33ef7SCédric Le Goater * This program is free software; you can redistribute it and/or modify 838da33ef7SCédric Le Goater * it under the terms of the GNU General Public License version 2 as 848da33ef7SCédric Le Goater * published by the Free Software Foundation. 858da33ef7SCédric Le Goater * 868da33ef7SCédric Le Goater * History : 878da33ef7SCédric Le Goater * 1. 2012/12/29 Ryan Chen Create 888da33ef7SCédric Le Goater */ 898da33ef7SCédric Le Goater 90fda9aaa6SCédric Le Goater /* SCU08 Clock Selection Register 91fda9aaa6SCédric Le Goater * 92fda9aaa6SCédric Le Goater * 31 Enable Video Engine clock dynamic slow down 93fda9aaa6SCédric Le Goater * 30:28 Video Engine clock slow down setting 94fda9aaa6SCédric Le Goater * 27 2D Engine GCLK clock source selection 95fda9aaa6SCédric Le Goater * 26 2D Engine GCLK clock throttling enable 96fda9aaa6SCédric Le Goater * 25:23 APB PCLK divider selection 97fda9aaa6SCédric Le Goater * 22:20 LPC Host LHCLK divider selection 98fda9aaa6SCédric Le Goater * 19 LPC Host LHCLK clock generation/output enable control 99fda9aaa6SCédric Le Goater * 18:16 MAC AHB bus clock divider selection 100fda9aaa6SCédric Le Goater * 15 SD/SDIO clock running enable 101fda9aaa6SCédric Le Goater * 14:12 SD/SDIO divider selection 102fda9aaa6SCédric Le Goater * 11 Reserved 103fda9aaa6SCédric Le Goater * 10:8 Video port output clock delay control bit 104fda9aaa6SCédric Le Goater * 7 ARM CPU/AHB clock slow down enable 105fda9aaa6SCédric Le Goater * 6:4 ARM CPU/AHB clock slow down setting 106fda9aaa6SCédric Le Goater * 3:2 ECLK clock source selection 107fda9aaa6SCédric Le Goater * 1 CPU/AHB clock slow down idle timer 108fda9aaa6SCédric Le Goater * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4]) 109fda9aaa6SCédric Le Goater */ 110fda9aaa6SCédric Le Goater #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7) 111fda9aaa6SCédric Le Goater 112fda9aaa6SCédric Le Goater /* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC) 113fda9aaa6SCédric Le Goater * 114fda9aaa6SCédric Le Goater * 18 H-PLL parameter selection 115fda9aaa6SCédric Le Goater * 0: Select H-PLL by strapping resistors 116fda9aaa6SCédric Le Goater * 1: Select H-PLL by the programmed registers (SCU24[17:0]) 117fda9aaa6SCédric Le Goater * 17 Enable H-PLL bypass mode 118fda9aaa6SCédric Le Goater * 16 Turn off H-PLL 119fda9aaa6SCédric Le Goater * 10:5 H-PLL Numerator 120fda9aaa6SCédric Le Goater * 4 H-PLL Output Divider 121fda9aaa6SCédric Le Goater * 3:0 H-PLL Denumerator 122fda9aaa6SCédric Le Goater * 123fda9aaa6SCédric Le Goater * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)] 124fda9aaa6SCédric Le Goater */ 125fda9aaa6SCédric Le Goater 126fda9aaa6SCédric Le Goater #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18) 127fda9aaa6SCédric Le Goater #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17) 128fda9aaa6SCédric Le Goater #define SCU_AST2400_H_PLL_OFF (0x1 << 16) 129fda9aaa6SCédric Le Goater 130fda9aaa6SCédric Le Goater /* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC) 131fda9aaa6SCédric Le Goater * 132fda9aaa6SCédric Le Goater * 21 Enable H-PLL reset 133fda9aaa6SCédric Le Goater * 20 Enable H-PLL bypass mode 134fda9aaa6SCédric Le Goater * 19 Turn off H-PLL 135fda9aaa6SCédric Le Goater * 18:13 H-PLL Post Divider 136fda9aaa6SCédric Le Goater * 12:5 H-PLL Numerator (M) 137fda9aaa6SCédric Le Goater * 4:0 H-PLL Denumerator (N) 138fda9aaa6SCédric Le Goater * 139fda9aaa6SCédric Le Goater * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1) 140fda9aaa6SCédric Le Goater * 141fda9aaa6SCédric Le Goater * The default frequency is 792Mhz when CLKIN = 24MHz 142fda9aaa6SCédric Le Goater */ 143fda9aaa6SCédric Le Goater 144fda9aaa6SCédric Le Goater #define SCU_H_PLL_BYPASS_EN (0x1 << 20) 145fda9aaa6SCédric Le Goater #define SCU_H_PLL_OFF (0x1 << 19) 146fda9aaa6SCédric Le Goater 147fda9aaa6SCédric Le Goater /* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC) 1488da33ef7SCédric Le Goater * 1498da33ef7SCédric Le Goater * 31:29 Software defined strapping registers 1508da33ef7SCédric Le Goater * 28:27 DRAM size setting (for VGA driver use) 1518da33ef7SCédric Le Goater * 26:24 DRAM configuration setting 1528da33ef7SCédric Le Goater * 23 Enable 25 MHz reference clock input 1538da33ef7SCédric Le Goater * 22 Enable GPIOE pass-through mode 1548da33ef7SCédric Le Goater * 21 Enable GPIOD pass-through mode 1558da33ef7SCédric Le Goater * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 1568da33ef7SCédric Le Goater * 19 Disable ACPI function 1578da33ef7SCédric Le Goater * 23,18 Clock source selection 1588da33ef7SCédric Le Goater * 17 Enable BMC 2nd boot watchdog timer 1598da33ef7SCédric Le Goater * 16 SuperIO configuration address selection 1608da33ef7SCédric Le Goater * 15 VGA Class Code selection 1618da33ef7SCédric Le Goater * 14 Enable LPC dedicated reset pin function 1628da33ef7SCédric Le Goater * 13:12 SPI mode selection 1638da33ef7SCédric Le Goater * 11:10 CPU/AHB clock frequency ratio selection 1648da33ef7SCédric Le Goater * 9:8 H-PLL default clock frequency selection 1658da33ef7SCédric Le Goater * 7 Define MAC#2 interface 1668da33ef7SCédric Le Goater * 6 Define MAC#1 interface 1678da33ef7SCédric Le Goater * 5 Enable VGA BIOS ROM 1688da33ef7SCédric Le Goater * 4 Boot flash memory extended option 1698da33ef7SCédric Le Goater * 3:2 VGA memory size selection 1708da33ef7SCédric Le Goater * 1:0 BMC CPU boot code selection 1718da33ef7SCédric Le Goater */ 1728da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 1738da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 1748da33ef7SCédric Le Goater 1758da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 1768da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 1778da33ef7SCédric Le Goater #define DRAM_SIZE_64MB 0 1788da33ef7SCédric Le Goater #define DRAM_SIZE_128MB 1 1798da33ef7SCédric Le Goater #define DRAM_SIZE_256MB 2 1808da33ef7SCédric Le Goater #define DRAM_SIZE_512MB 3 1818da33ef7SCédric Le Goater 1828da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 1838da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 1848da33ef7SCédric Le Goater 1858da33ef7SCédric Le Goater #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 1868da33ef7SCédric Le Goater #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 1878da33ef7SCédric Le Goater #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 1888da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 1898da33ef7SCédric Le Goater 1908da33ef7SCédric Le Goater /* bit 23, 18 [1,0] */ 1918da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 1928da33ef7SCédric Le Goater | (((x) & 0x1) << 18)) 1938da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 1948da33ef7SCédric Le Goater | (((x) >> 18) & 0x1)) 1958da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 196fda9aaa6SCédric Le Goater #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23) 1978da33ef7SCédric Le Goater #define AST2400_CLK_24M_IN 0 1988da33ef7SCédric Le Goater #define AST2400_CLK_48M_IN 1 1998da33ef7SCédric Le Goater #define AST2400_CLK_25M_IN_24M_USB_CKI 2 2008da33ef7SCédric Le Goater #define AST2400_CLK_25M_IN_48M_USB_CKI 3 2018da33ef7SCédric Le Goater 202fda9aaa6SCédric Le Goater #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18) 2038da33ef7SCédric Le Goater #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 2048da33ef7SCédric Le Goater #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 2058da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 2068da33ef7SCédric Le Goater #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 2078da33ef7SCédric Le Goater 2088da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 2098da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 2108da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_DIS 0 2118da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_MASTER 1 2128da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_M_S_EN 2 2138da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 2148da33ef7SCédric Le Goater 2158da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 2168da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 2178da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 2188da33ef7SCédric Le Goater #define AST2400_CPU_AHB_RATIO_1_1 0 2198da33ef7SCédric Le Goater #define AST2400_CPU_AHB_RATIO_2_1 1 2208da33ef7SCédric Le Goater #define AST2400_CPU_AHB_RATIO_4_1 2 2218da33ef7SCédric Le Goater #define AST2400_CPU_AHB_RATIO_3_1 3 2228da33ef7SCédric Le Goater 2238da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 2248da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 2258da33ef7SCédric Le Goater #define AST2400_CPU_384MHZ 0 2268da33ef7SCédric Le Goater #define AST2400_CPU_360MHZ 1 2278da33ef7SCédric Le Goater #define AST2400_CPU_336MHZ 2 2288da33ef7SCédric Le Goater #define AST2400_CPU_408MHZ 3 2298da33ef7SCédric Le Goater 2308da33ef7SCédric Le Goater #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 2318da33ef7SCédric Le Goater #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 2328da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 2338da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 2348da33ef7SCédric Le Goater 2358da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 2368da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 2378da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 2388da33ef7SCédric Le Goater #define VGA_8M_DRAM 0 2398da33ef7SCédric Le Goater #define VGA_16M_DRAM 1 2408da33ef7SCédric Le Goater #define VGA_32M_DRAM 2 2418da33ef7SCédric Le Goater #define VGA_64M_DRAM 3 2428da33ef7SCédric Le Goater 2438da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 2448da33ef7SCédric Le Goater #define AST2400_NOR_BOOT 0 2458da33ef7SCédric Le Goater #define AST2400_NAND_BOOT 1 2468da33ef7SCédric Le Goater #define AST2400_SPI_BOOT 2 2478da33ef7SCédric Le Goater #define AST2400_DIS_BOOT 3 2488da33ef7SCédric Le Goater 249365aff1eSCédric Le Goater /* 250fda9aaa6SCédric Le Goater * SCU70 Hardware strapping register definition (for Aspeed AST2500 251fda9aaa6SCédric Le Goater * SoC and higher) 252365aff1eSCédric Le Goater * 253365aff1eSCédric Le Goater * 31 Enable SPI Flash Strap Auto Fetch Mode 254365aff1eSCédric Le Goater * 30 Enable GPIO Strap Mode 255365aff1eSCédric Le Goater * 29 Select UART Debug Port 256365aff1eSCédric Le Goater * 28 Reserved (1) 257365aff1eSCédric Le Goater * 27 Enable fast reset mode for ARM ICE debugger 258365aff1eSCédric Le Goater * 26 Enable eSPI flash mode 259365aff1eSCédric Le Goater * 25 Enable eSPI mode 260365aff1eSCédric Le Goater * 24 Select DDR4 SDRAM 261365aff1eSCédric Le Goater * 23 Select 25 MHz reference clock input mode 262365aff1eSCédric Le Goater * 22 Enable GPIOE pass-through mode 263365aff1eSCédric Le Goater * 21 Enable GPIOD pass-through mode 264365aff1eSCédric Le Goater * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 265365aff1eSCédric Le Goater * 19 Enable ACPI function 266365aff1eSCédric Le Goater * 18 Select USBCKI input frequency 267365aff1eSCédric Le Goater * 17 Enable BMC 2nd boot watchdog timer 268365aff1eSCédric Le Goater * 16 SuperIO configuration address selection 269365aff1eSCédric Le Goater * 15 VGA Class Code selection 270365aff1eSCédric Le Goater * 14 Select dedicated LPC reset input 271365aff1eSCédric Le Goater * 13:12 SPI mode selection 272365aff1eSCédric Le Goater * 11:9 AXI/AHB clock frequency ratio selection 273365aff1eSCédric Le Goater * 8 Reserved (0) 274365aff1eSCédric Le Goater * 7 Define MAC#2 interface 275365aff1eSCédric Le Goater * 6 Define MAC#1 interface 276365aff1eSCédric Le Goater * 5 Enable dedicated VGA BIOS ROM 277365aff1eSCédric Le Goater * 4 Reserved (0) 278365aff1eSCédric Le Goater * 3:2 VGA memory size selection 279365aff1eSCédric Le Goater * 1 Reserved (1) 280365aff1eSCédric Le Goater * 0 Disable CPU boot 281365aff1eSCédric Le Goater */ 282365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31) 283365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30) 284365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29) 285365aff1eSCédric Le Goater #define UART_DEBUG_UART1 0 286365aff1eSCédric Le Goater #define UART_DEBUG_UART5 1 287365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28) 288365aff1eSCédric Le Goater 289365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27) 290365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26) 291365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25) 292365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24) 293d98c48a1SIgor Kononenko #define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23) 294365aff1eSCédric Le Goater 295365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19) 296365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18) 297365aff1eSCédric Le Goater #define USBCKI_FREQ_24MHZ 0 298365aff1eSCédric Le Goater #define USBCKI_FREQ_28MHZ 1 299365aff1eSCédric Le Goater 300365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9) 301365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7) 302365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9) 303365aff1eSCédric Le Goater #define AXI_AHB_RATIO_UNDEFINED 0 304365aff1eSCédric Le Goater #define AXI_AHB_RATIO_2_1 1 305365aff1eSCédric Le Goater #define AXI_AHB_RATIO_3_1 2 306365aff1eSCédric Le Goater #define AXI_AHB_RATIO_4_1 3 307365aff1eSCédric Le Goater #define AXI_AHB_RATIO_5_1 4 308365aff1eSCédric Le Goater #define AXI_AHB_RATIO_6_1 5 309365aff1eSCédric Le Goater #define AXI_AHB_RATIO_7_1 6 310365aff1eSCédric Le Goater #define AXI_AHB_RATIO_8_1 7 311365aff1eSCédric Le Goater 312365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1) 313365aff1eSCédric Le Goater #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0) 314365aff1eSCédric Le Goater 315365aff1eSCédric Le Goater #define AST2500_HW_STRAP1_DEFAULTS ( \ 316365aff1eSCédric Le Goater SCU_AST2500_HW_STRAP_RESERVED28 | \ 317365aff1eSCédric Le Goater SCU_HW_STRAP_2ND_BOOT_WDT | \ 318365aff1eSCédric Le Goater SCU_HW_STRAP_VGA_CLASS_CODE | \ 319365aff1eSCédric Le Goater SCU_HW_STRAP_LPC_RESET_PIN | \ 320365aff1eSCédric Le Goater SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ 321365aff1eSCédric Le Goater SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ 322365aff1eSCédric Le Goater SCU_AST2500_HW_STRAP_RESERVED1) 323365aff1eSCédric Le Goater 324dd7f19a9SSteven Lee /* 325dd7f19a9SSteven Lee * SCU200 H-PLL Parameter Register (for Aspeed AST2600 SOC) 326dd7f19a9SSteven Lee * 327dd7f19a9SSteven Lee * 28:26 H-PLL Parameters 328dd7f19a9SSteven Lee * 25 Enable H-PLL reset 329dd7f19a9SSteven Lee * 24 Enable H-PLL bypass mode 330dd7f19a9SSteven Lee * 23 Turn off H-PLL 331dd7f19a9SSteven Lee * 22:19 H-PLL Post Divider (P) 332dd7f19a9SSteven Lee * 18:13 H-PLL Numerator (M) 333dd7f19a9SSteven Lee * 12:0 H-PLL Denumerator (N) 334dd7f19a9SSteven Lee * 335dd7f19a9SSteven Lee * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1) 336dd7f19a9SSteven Lee * 337dd7f19a9SSteven Lee * The default frequency is 1200Mhz when CLKIN = 25MHz 338dd7f19a9SSteven Lee */ 339dd7f19a9SSteven Lee #define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24) 340dd7f19a9SSteven Lee #define SCU_AST2600_H_PLL_OFF (0x1 << 23) 341dd7f19a9SSteven Lee 342*fa541a60SSteven Lee /* 343*fa541a60SSteven Lee * SCU310 Clock Selection Register Set 4 (for Aspeed AST1030 SOC) 344*fa541a60SSteven Lee * 345*fa541a60SSteven Lee * 31 I3C Clock Source selection 346*fa541a60SSteven Lee * 30:28 I3C clock divider selection 347*fa541a60SSteven Lee * 26:24 MAC AHB clock divider selection 348*fa541a60SSteven Lee * 22:20 RGMII 125MHz clock divider ration 349*fa541a60SSteven Lee * 19:16 RGMII 50MHz clock divider ration 350*fa541a60SSteven Lee * 15 LHCLK clock generation/output enable control 351*fa541a60SSteven Lee * 14:12 LHCLK divider selection 352*fa541a60SSteven Lee * 11:8 APB Bus PCLK divider selection 353*fa541a60SSteven Lee * 7 Select PECI clock source 354*fa541a60SSteven Lee * 6 Select UART debug port clock source 355*fa541a60SSteven Lee * 5 Select UART6 clock source 356*fa541a60SSteven Lee * 4 Select UART5 clock source 357*fa541a60SSteven Lee * 3 Select UART4 clock source 358*fa541a60SSteven Lee * 2 Select UART3 clock source 359*fa541a60SSteven Lee * 1 Select UART2 clock source 360*fa541a60SSteven Lee * 0 Select UART1 clock source 361*fa541a60SSteven Lee */ 362*fa541a60SSteven Lee #define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf) 363*fa541a60SSteven Lee 3641c8a2388SAndrew Jeffery #endif /* ASPEED_SCU_H */ 365