11c8a2388SAndrew Jeffery /* 21c8a2388SAndrew Jeffery * ASPEED System Control Unit 31c8a2388SAndrew Jeffery * 41c8a2388SAndrew Jeffery * Andrew Jeffery <andrew@aj.id.au> 51c8a2388SAndrew Jeffery * 61c8a2388SAndrew Jeffery * Copyright 2016 IBM Corp. 71c8a2388SAndrew Jeffery * 81c8a2388SAndrew Jeffery * This code is licensed under the GPL version 2 or later. See 91c8a2388SAndrew Jeffery * the COPYING file in the top-level directory. 101c8a2388SAndrew Jeffery */ 111c8a2388SAndrew Jeffery #ifndef ASPEED_SCU_H 121c8a2388SAndrew Jeffery #define ASPEED_SCU_H 131c8a2388SAndrew Jeffery 141c8a2388SAndrew Jeffery #include "hw/sysbus.h" 151c8a2388SAndrew Jeffery 161c8a2388SAndrew Jeffery #define TYPE_ASPEED_SCU "aspeed.scu" 171c8a2388SAndrew Jeffery #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) 181c8a2388SAndrew Jeffery 191c8a2388SAndrew Jeffery #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) 201c8a2388SAndrew Jeffery 211c8a2388SAndrew Jeffery typedef struct AspeedSCUState { 221c8a2388SAndrew Jeffery /*< private >*/ 231c8a2388SAndrew Jeffery SysBusDevice parent_obj; 241c8a2388SAndrew Jeffery 251c8a2388SAndrew Jeffery /*< public >*/ 261c8a2388SAndrew Jeffery MemoryRegion iomem; 271c8a2388SAndrew Jeffery 281c8a2388SAndrew Jeffery uint32_t regs[ASPEED_SCU_NR_REGS]; 291c8a2388SAndrew Jeffery uint32_t silicon_rev; 301c8a2388SAndrew Jeffery uint32_t hw_strap1; 311c8a2388SAndrew Jeffery uint32_t hw_strap2; 321c8a2388SAndrew Jeffery } AspeedSCUState; 331c8a2388SAndrew Jeffery 3479a9f323SCédric Le Goater #define AST2400_A0_SILICON_REV 0x02000303U 3579a9f323SCédric Le Goater #define AST2500_A0_SILICON_REV 0x04000303U 3679a9f323SCédric Le Goater 3779a9f323SCédric Le Goater extern bool is_supported_silicon_rev(uint32_t silicon_rev); 3879a9f323SCédric Le Goater 39*8da33ef7SCédric Le Goater /* 40*8da33ef7SCédric Le Goater * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions 41*8da33ef7SCédric Le Goater * were added. 42*8da33ef7SCédric Le Goater * 43*8da33ef7SCédric Le Goater * Original header file : 44*8da33ef7SCédric Le Goater * arch/arm/mach-aspeed/include/mach/regs-scu.h 45*8da33ef7SCédric Le Goater * 46*8da33ef7SCédric Le Goater * Copyright (C) 2012-2020 ASPEED Technology Inc. 47*8da33ef7SCédric Le Goater * 48*8da33ef7SCédric Le Goater * This program is free software; you can redistribute it and/or modify 49*8da33ef7SCédric Le Goater * it under the terms of the GNU General Public License version 2 as 50*8da33ef7SCédric Le Goater * published by the Free Software Foundation. 51*8da33ef7SCédric Le Goater * 52*8da33ef7SCédric Le Goater * History : 53*8da33ef7SCédric Le Goater * 1. 2012/12/29 Ryan Chen Create 54*8da33ef7SCédric Le Goater */ 55*8da33ef7SCédric Le Goater 56*8da33ef7SCédric Le Goater /* Hardware Strapping Register definition (for Aspeed AST2400 SOC) 57*8da33ef7SCédric Le Goater * 58*8da33ef7SCédric Le Goater * 31:29 Software defined strapping registers 59*8da33ef7SCédric Le Goater * 28:27 DRAM size setting (for VGA driver use) 60*8da33ef7SCédric Le Goater * 26:24 DRAM configuration setting 61*8da33ef7SCédric Le Goater * 23 Enable 25 MHz reference clock input 62*8da33ef7SCédric Le Goater * 22 Enable GPIOE pass-through mode 63*8da33ef7SCédric Le Goater * 21 Enable GPIOD pass-through mode 64*8da33ef7SCédric Le Goater * 20 Disable LPC to decode SuperIO 0x2E/0x4E address 65*8da33ef7SCédric Le Goater * 19 Disable ACPI function 66*8da33ef7SCédric Le Goater * 23,18 Clock source selection 67*8da33ef7SCédric Le Goater * 17 Enable BMC 2nd boot watchdog timer 68*8da33ef7SCédric Le Goater * 16 SuperIO configuration address selection 69*8da33ef7SCédric Le Goater * 15 VGA Class Code selection 70*8da33ef7SCédric Le Goater * 14 Enable LPC dedicated reset pin function 71*8da33ef7SCédric Le Goater * 13:12 SPI mode selection 72*8da33ef7SCédric Le Goater * 11:10 CPU/AHB clock frequency ratio selection 73*8da33ef7SCédric Le Goater * 9:8 H-PLL default clock frequency selection 74*8da33ef7SCédric Le Goater * 7 Define MAC#2 interface 75*8da33ef7SCédric Le Goater * 6 Define MAC#1 interface 76*8da33ef7SCédric Le Goater * 5 Enable VGA BIOS ROM 77*8da33ef7SCédric Le Goater * 4 Boot flash memory extended option 78*8da33ef7SCédric Le Goater * 3:2 VGA memory size selection 79*8da33ef7SCédric Le Goater * 1:0 BMC CPU boot code selection 80*8da33ef7SCédric Le Goater */ 81*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29) 82*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29) 83*8da33ef7SCédric Le Goater 84*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27) 85*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27) 86*8da33ef7SCédric Le Goater #define DRAM_SIZE_64MB 0 87*8da33ef7SCédric Le Goater #define DRAM_SIZE_128MB 1 88*8da33ef7SCédric Le Goater #define DRAM_SIZE_256MB 2 89*8da33ef7SCédric Le Goater #define DRAM_SIZE_512MB 3 90*8da33ef7SCédric Le Goater 91*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24) 92*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24) 93*8da33ef7SCédric Le Goater 94*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22) 95*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21) 96*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20) 97*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19) 98*8da33ef7SCédric Le Goater 99*8da33ef7SCédric Le Goater /* bit 23, 18 [1,0] */ 100*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \ 101*8da33ef7SCédric Le Goater | (((x) & 0x1) << 18)) 102*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \ 103*8da33ef7SCédric Le Goater | (((x) >> 18) & 0x1)) 104*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18)) 105*8da33ef7SCédric Le Goater #define AST2400_CLK_25M_IN (0x1 << 23) 106*8da33ef7SCédric Le Goater #define AST2400_CLK_24M_IN 0 107*8da33ef7SCédric Le Goater #define AST2400_CLK_48M_IN 1 108*8da33ef7SCédric Le Goater #define AST2400_CLK_25M_IN_24M_USB_CKI 2 109*8da33ef7SCédric Le Goater #define AST2400_CLK_25M_IN_48M_USB_CKI 3 110*8da33ef7SCédric Le Goater 111*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17) 112*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16) 113*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15) 114*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14) 115*8da33ef7SCédric Le Goater 116*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12) 117*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12) 118*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_DIS 0 119*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_MASTER 1 120*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_M_S_EN 2 121*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_PASS_THROUGH 3 122*8da33ef7SCédric Le Goater 123*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10) 124*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3) 125*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10) 126*8da33ef7SCédric Le Goater #define AST2400_CPU_AHB_RATIO_1_1 0 127*8da33ef7SCédric Le Goater #define AST2400_CPU_AHB_RATIO_2_1 1 128*8da33ef7SCédric Le Goater #define AST2400_CPU_AHB_RATIO_4_1 2 129*8da33ef7SCédric Le Goater #define AST2400_CPU_AHB_RATIO_3_1 3 130*8da33ef7SCédric Le Goater 131*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3) 132*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8) 133*8da33ef7SCédric Le Goater #define AST2400_CPU_384MHZ 0 134*8da33ef7SCédric Le Goater #define AST2400_CPU_360MHZ 1 135*8da33ef7SCédric Le Goater #define AST2400_CPU_336MHZ 2 136*8da33ef7SCédric Le Goater #define AST2400_CPU_408MHZ 3 137*8da33ef7SCédric Le Goater 138*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7) 139*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6) 140*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5) 141*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4) 142*8da33ef7SCédric Le Goater 143*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3) 144*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_MASK (0x3 << 2) 145*8da33ef7SCédric Le Goater #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2) 146*8da33ef7SCédric Le Goater #define VGA_8M_DRAM 0 147*8da33ef7SCédric Le Goater #define VGA_16M_DRAM 1 148*8da33ef7SCédric Le Goater #define VGA_32M_DRAM 2 149*8da33ef7SCédric Le Goater #define VGA_64M_DRAM 3 150*8da33ef7SCédric Le Goater 151*8da33ef7SCédric Le Goater #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x) 152*8da33ef7SCédric Le Goater #define AST2400_NOR_BOOT 0 153*8da33ef7SCédric Le Goater #define AST2400_NAND_BOOT 1 154*8da33ef7SCédric Le Goater #define AST2400_SPI_BOOT 2 155*8da33ef7SCédric Le Goater #define AST2400_DIS_BOOT 3 156*8da33ef7SCédric Le Goater 1571c8a2388SAndrew Jeffery #endif /* ASPEED_SCU_H */ 158