1 /* 2 * ASPEED Hash and Crypto Engine 3 * 4 * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates 5 * Copyright (C) 2021 IBM Corp. 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 */ 9 10 #ifndef ASPEED_HACE_H 11 #define ASPEED_HACE_H 12 13 #include "hw/sysbus.h" 14 #include "crypto/hash.h" 15 16 #define TYPE_ASPEED_HACE "aspeed.hace" 17 #define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400" 18 #define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500" 19 #define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600" 20 #define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030" 21 22 OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) 23 24 #define ASPEED_HACE_NR_REGS (0x64 >> 2) 25 #define ASPEED_HACE_MAX_SG 256 /* max number of entries */ 26 27 struct AspeedHACEState { 28 SysBusDevice parent; 29 30 MemoryRegion iomem; 31 qemu_irq irq; 32 33 struct iovec iov_cache[ASPEED_HACE_MAX_SG]; 34 uint32_t regs[ASPEED_HACE_NR_REGS]; 35 uint32_t total_req_len; 36 uint32_t iov_count; 37 38 MemoryRegion *dram_mr; 39 AddressSpace dram_as; 40 41 QCryptoHash *hash_ctx; 42 }; 43 44 45 struct AspeedHACEClass { 46 SysBusDeviceClass parent_class; 47 48 uint32_t src_mask; 49 uint32_t dest_mask; 50 uint32_t key_mask; 51 uint32_t hash_mask; 52 }; 53 54 #endif /* ASPEED_HACE_H */ 55