1 /*
2  * Allwinner A10 DRAM Controller emulation
3  *
4  * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
5  *
6  *  This file is derived from Allwinner H3 DRAMC,
7  *  by Niek Linnenbank.
8  *
9  * This program is free software: you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation, either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22 
23 #ifndef HW_MISC_ALLWINNER_A10_DRAMC_H
24 #define HW_MISC_ALLWINNER_A10_DRAMC_H
25 
26 #include "qom/object.h"
27 #include "hw/sysbus.h"
28 #include "hw/register.h"
29 
30 /**
31  * @name Constants
32  * @{
33  */
34 
35 /** Size of register I/O address space used by DRAMC device */
36 #define AW_A10_DRAMC_IOSIZE        (0x1000)
37 
38 /** Total number of known registers */
39 #define AW_A10_DRAMC_REGS_NUM      (AW_A10_DRAMC_IOSIZE / sizeof(uint32_t))
40 
41 /** @} */
42 
43 /**
44  * @name Object model
45  * @{
46  */
47 
48 #define TYPE_AW_A10_DRAMC    "allwinner-a10-dramc"
49 OBJECT_DECLARE_SIMPLE_TYPE(AwA10DramControllerState, AW_A10_DRAMC)
50 
51 /** @} */
52 
53 /**
54  * Allwinner A10 DRAMC object instance state.
55  */
56 struct AwA10DramControllerState {
57     /*< private >*/
58     SysBusDevice parent_obj;
59     /*< public >*/
60 
61     /** Maps I/O registers in physical memory */
62     MemoryRegion iomem;
63 
64     /** Array of hardware registers */
65     uint32_t regs[AW_A10_DRAMC_REGS_NUM];
66 };
67 
68 #endif /* HW_MISC_ALLWINNER_A10_DRAMC_H */
69