xref: /openbmc/qemu/include/hw/mips/cps.h (revision 6a0acfff)
1 /*
2  * Coherent Processing System emulation.
3  *
4  * Copyright (c) 2016 Imagination Technologies
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef MIPS_CPS_H
21 #define MIPS_CPS_H
22 
23 #include "hw/sysbus.h"
24 #include "hw/misc/mips_cmgcr.h"
25 #include "hw/intc/mips_gic.h"
26 #include "hw/misc/mips_cpc.h"
27 #include "hw/misc/mips_itu.h"
28 #include "target/mips/cpu.h"
29 
30 #define TYPE_MIPS_CPS "mips-cps"
31 #define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
32 
33 typedef struct MIPSCPSState {
34     SysBusDevice parent_obj;
35 
36     uint32_t num_vp;
37     uint32_t num_irq;
38     char *cpu_type;
39 
40     MemoryRegion container;
41     MIPSGCRState gcr;
42     MIPSGICState gic;
43     MIPSCPCState cpc;
44     MIPSITUState itu;
45 } MIPSCPSState;
46 
47 qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
48 
49 #endif
50