xref: /openbmc/qemu/include/hw/isa/i8259_internal.h (revision 05caa062)
1 /*
2  * QEMU 8259 - internal interfaces
3  *
4  * Copyright (c) 2011 Jan Kiszka, Siemens AG
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #ifndef QEMU_I8259_INTERNAL_H
26 #define QEMU_I8259_INTERNAL_H
27 
28 #include "hw/isa/isa.h"
29 #include "hw/intc/intc.h"
30 #include "hw/intc/i8259.h"
31 #include "qom/object.h"
32 
33 
34 #define TYPE_PIC_COMMON "pic-common"
35 OBJECT_DECLARE_TYPE(PICCommonState, PICCommonClass, PIC_COMMON)
36 
37 struct PICCommonClass {
38     DeviceClass parent_class;
39 
40     void (*pre_save)(PICCommonState *s);
41     void (*post_load)(PICCommonState *s);
42 };
43 
44 struct PICCommonState {
45     ISADevice parent_obj;
46 
47     uint8_t last_irr; /* edge detection */
48     uint8_t irr; /* interrupt request register */
49     uint8_t imr; /* interrupt mask register */
50     uint8_t isr; /* interrupt service register */
51     uint8_t priority_add; /* highest irq priority */
52     uint8_t irq_base;
53     uint8_t read_reg_select;
54     uint8_t poll;
55     uint8_t special_mask;
56     uint8_t init_state;
57     uint8_t auto_eoi;
58     uint8_t rotate_on_auto_eoi;
59     uint8_t special_fully_nested_mode;
60     uint8_t init4; /* true if 4 byte init */
61     uint8_t single_mode; /* true if slave pic is not initialized */
62     uint8_t elcr; /* PIIX edge/trigger selection*/
63     uint8_t elcr_mask;
64     uint8_t ltim; /* Edge/Level Bank Select (pre-PIIX, chip-wide) */
65     qemu_irq int_out[1];
66     uint32_t master; /* reflects /SP input pin */
67     uint32_t iobase;
68     uint32_t elcr_addr;
69     MemoryRegion base_io;
70     MemoryRegion elcr_io;
71 };
72 
73 void pic_reset_common(PICCommonState *s);
74 ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master);
75 void pic_stat_update_irq(int irq, int level);
76 
77 #endif /* QEMU_I8259_INTERNAL_H */
78