1 /*
2  * QEMU model of Xilinx I/O Module Interrupt Controller
3  *
4  * Copyright (c) 2014 Xilinx Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #ifndef XLNX_PMU_IO_INTC_H
26 #define XLNX_PMU_IO_INTC_H
27 
28 #include "qemu/osdep.h"
29 #include "hw/sysbus.h"
30 #include "hw/register.h"
31 
32 #define TYPE_XLNX_PMU_IO_INTC "xlnx.pmu_io_intc"
33 
34 #define XLNX_PMU_IO_INTC(obj) \
35      OBJECT_CHECK(XlnxPMUIOIntc, (obj), TYPE_XLNX_PMU_IO_INTC)
36 
37 /* This is R_PIT3_CONTROL + 1 */
38 #define XLNXPMUIOINTC_R_MAX (0x78 + 1)
39 
40 typedef struct XlnxPMUIOIntc {
41     SysBusDevice parent_obj;
42     MemoryRegion iomem;
43 
44     qemu_irq parent_irq;
45 
46     struct {
47         uint32_t intr_size;
48         uint32_t level_edge;
49         uint32_t positive;
50     } cfg;
51 
52     uint32_t irq_raw;
53 
54     uint32_t regs[XLNXPMUIOINTC_R_MAX];
55     RegisterInfo regs_info[XLNXPMUIOINTC_R_MAX];
56 } XlnxPMUIOIntc;
57 
58 #endif /* XLNX_PMU_IO_INTC_H */
59