1 /* 2 * RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface 3 * 4 * Copyright (c) 2021 Western Digital Corporation or its affiliates. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_RISCV_IMSIC_H 20 #define HW_RISCV_IMSIC_H 21 22 #include "hw/sysbus.h" 23 #include "qom/object.h" 24 25 #define TYPE_RISCV_IMSIC "riscv.imsic" 26 27 typedef struct RISCVIMSICState RISCVIMSICState; 28 DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC) 29 30 #define IMSIC_MMIO_PAGE_SHIFT 12 31 #define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) 32 #define IMSIC_MMIO_SIZE(__num_pages) ((__num_pages) * IMSIC_MMIO_PAGE_SZ) 33 34 #define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6 35 #define IMSIC_MMIO_GROUP_MIN_SHIFT 24 36 37 #define IMSIC_HART_NUM_GUESTS(__guest_bits) \ 38 (1U << (__guest_bits)) 39 #define IMSIC_HART_SIZE(__guest_bits) \ 40 (IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ) 41 #define IMSIC_GROUP_NUM_HARTS(__hart_bits) \ 42 (1U << (__hart_bits)) 43 #define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits) \ 44 (IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits)) 45 46 struct RISCVIMSICState { 47 /*< private >*/ 48 SysBusDevice parent_obj; 49 qemu_irq *external_irqs; 50 51 /*< public >*/ 52 MemoryRegion mmio; 53 uint32_t num_eistate; 54 uint32_t *eidelivery; 55 uint32_t *eithreshold; 56 uint32_t *eistate; 57 58 /* config */ 59 bool mmode; 60 uint32_t hartid; 61 uint32_t num_pages; 62 uint32_t num_irqs; 63 }; 64 65 DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, 66 uint32_t num_pages, uint32_t num_ids); 67 68 #endif 69