1*9746e583SAnup Patel /* 2*9746e583SAnup Patel * RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface 3*9746e583SAnup Patel * 4*9746e583SAnup Patel * Copyright (c) 2021 Western Digital Corporation or its affiliates. 5*9746e583SAnup Patel * 6*9746e583SAnup Patel * This program is free software; you can redistribute it and/or modify it 7*9746e583SAnup Patel * under the terms and conditions of the GNU General Public License, 8*9746e583SAnup Patel * version 2 or later, as published by the Free Software Foundation. 9*9746e583SAnup Patel * 10*9746e583SAnup Patel * This program is distributed in the hope it will be useful, but WITHOUT 11*9746e583SAnup Patel * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*9746e583SAnup Patel * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*9746e583SAnup Patel * more details. 14*9746e583SAnup Patel * 15*9746e583SAnup Patel * You should have received a copy of the GNU General Public License along with 16*9746e583SAnup Patel * this program. If not, see <http://www.gnu.org/licenses/>. 17*9746e583SAnup Patel */ 18*9746e583SAnup Patel 19*9746e583SAnup Patel #ifndef HW_RISCV_IMSIC_H 20*9746e583SAnup Patel #define HW_RISCV_IMSIC_H 21*9746e583SAnup Patel 22*9746e583SAnup Patel #include "hw/sysbus.h" 23*9746e583SAnup Patel #include "qom/object.h" 24*9746e583SAnup Patel 25*9746e583SAnup Patel #define TYPE_RISCV_IMSIC "riscv.imsic" 26*9746e583SAnup Patel 27*9746e583SAnup Patel typedef struct RISCVIMSICState RISCVIMSICState; 28*9746e583SAnup Patel DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC) 29*9746e583SAnup Patel 30*9746e583SAnup Patel #define IMSIC_MMIO_PAGE_SHIFT 12 31*9746e583SAnup Patel #define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) 32*9746e583SAnup Patel #define IMSIC_MMIO_SIZE(__num_pages) ((__num_pages) * IMSIC_MMIO_PAGE_SZ) 33*9746e583SAnup Patel 34*9746e583SAnup Patel #define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6 35*9746e583SAnup Patel #define IMSIC_MMIO_GROUP_MIN_SHIFT 24 36*9746e583SAnup Patel 37*9746e583SAnup Patel #define IMSIC_HART_NUM_GUESTS(__guest_bits) \ 38*9746e583SAnup Patel (1U << (__guest_bits)) 39*9746e583SAnup Patel #define IMSIC_HART_SIZE(__guest_bits) \ 40*9746e583SAnup Patel (IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ) 41*9746e583SAnup Patel #define IMSIC_GROUP_NUM_HARTS(__hart_bits) \ 42*9746e583SAnup Patel (1U << (__hart_bits)) 43*9746e583SAnup Patel #define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits) \ 44*9746e583SAnup Patel (IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits)) 45*9746e583SAnup Patel 46*9746e583SAnup Patel struct RISCVIMSICState { 47*9746e583SAnup Patel /*< private >*/ 48*9746e583SAnup Patel SysBusDevice parent_obj; 49*9746e583SAnup Patel qemu_irq *external_irqs; 50*9746e583SAnup Patel 51*9746e583SAnup Patel /*< public >*/ 52*9746e583SAnup Patel MemoryRegion mmio; 53*9746e583SAnup Patel uint32_t num_eistate; 54*9746e583SAnup Patel uint32_t *eidelivery; 55*9746e583SAnup Patel uint32_t *eithreshold; 56*9746e583SAnup Patel uint32_t *eistate; 57*9746e583SAnup Patel 58*9746e583SAnup Patel /* config */ 59*9746e583SAnup Patel bool mmode; 60*9746e583SAnup Patel uint32_t hartid; 61*9746e583SAnup Patel uint32_t num_pages; 62*9746e583SAnup Patel uint32_t num_irqs; 63*9746e583SAnup Patel }; 64*9746e583SAnup Patel 65*9746e583SAnup Patel DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, 66*9746e583SAnup Patel uint32_t num_pages, uint32_t num_ids); 67*9746e583SAnup Patel 68*9746e583SAnup Patel #endif 69