1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 7 * Copyright (C) 2016 Imagination Technologies 8 * 9 */ 10 11 #ifndef MIPS_GIC_H 12 #define MIPS_GIC_H 13 14 #include "hw/timer/mips_gictimer.h" 15 #include "cpu.h" 16 /* 17 * GIC Specific definitions 18 */ 19 20 /* The MIPS default location */ 21 #define GIC_BASE_ADDR 0x1bdc0000ULL 22 #define GIC_ADDRSPACE_SZ (128 * 1024) 23 24 /* Constants */ 25 #define GIC_POL_POS 1 26 #define GIC_POL_NEG 0 27 #define GIC_TRIG_EDGE 1 28 #define GIC_TRIG_LEVEL 0 29 30 #define MSK(n) ((1ULL << (n)) - 1) 31 32 /* GIC Address Space */ 33 #define SHARED_SECTION_OFS 0x0000 34 #define SHARED_SECTION_SIZE 0x8000 35 #define VP_LOCAL_SECTION_OFS 0x8000 36 #define VP_LOCAL_SECTION_SIZE 0x4000 37 #define VP_OTHER_SECTION_OFS 0xc000 38 #define VP_OTHER_SECTION_SIZE 0x4000 39 #define USM_VISIBLE_SECTION_OFS 0x10000 40 #define USM_VISIBLE_SECTION_SIZE 0x10000 41 42 /* Register Map for Shared Section */ 43 44 #define GIC_SH_CONFIG_OFS 0x0000 45 46 /* Shared Global Counter */ 47 #define GIC_SH_COUNTERLO_OFS 0x0010 48 #define GIC_SH_COUNTERHI_OFS 0x0014 49 #define GIC_SH_REVISIONID_OFS 0x0020 50 51 /* Set/Clear corresponding bit in Edge Detect Register */ 52 #define GIC_SH_WEDGE_OFS 0x0280 53 54 /* Reset Mask - Disables Interrupt */ 55 #define GIC_SH_RMASK_OFS 0x0300 56 #define GIC_SH_RMASK_LAST_OFS 0x031c 57 58 /* Set Mask (WO) - Enables Interrupt */ 59 #define GIC_SH_SMASK_OFS 0x0380 60 #define GIC_SH_SMASK_LAST_OFS 0x039c 61 62 /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ 63 #define GIC_SH_MASK_OFS 0x0400 64 #define GIC_SH_MASK_LAST_OFS 0x041c 65 66 /* Pending Global Interrupts (RO) */ 67 #define GIC_SH_PEND_OFS 0x0480 68 #define GIC_SH_PEND_LAST_OFS 0x049c 69 70 #define GIC_SH_MAP0_PIN_OFS 0x0500 71 #define GIC_SH_MAP255_PIN_OFS 0x08fc 72 73 #define GIC_SH_MAP0_VP_OFS 0x2000 74 #define GIC_SH_MAP255_VP_LAST_OFS 0x3fe4 75 76 /* Register Map for Local Section */ 77 #define GIC_VP_CTL_OFS 0x0000 78 #define GIC_VP_PEND_OFS 0x0004 79 #define GIC_VP_MASK_OFS 0x0008 80 #define GIC_VP_RMASK_OFS 0x000c 81 #define GIC_VP_SMASK_OFS 0x0010 82 #define GIC_VP_WD_MAP_OFS 0x0040 83 #define GIC_VP_COMPARE_MAP_OFS 0x0044 84 #define GIC_VP_TIMER_MAP_OFS 0x0048 85 #define GIC_VP_FDC_MAP_OFS 0x004c 86 #define GIC_VP_PERFCTR_MAP_OFS 0x0050 87 #define GIC_VP_SWINT0_MAP_OFS 0x0054 88 #define GIC_VP_SWINT1_MAP_OFS 0x0058 89 #define GIC_VP_OTHER_ADDR_OFS 0x0080 90 #define GIC_VP_IDENT_OFS 0x0088 91 #define GIC_VP_WD_CONFIG0_OFS 0x0090 92 #define GIC_VP_WD_COUNT0_OFS 0x0094 93 #define GIC_VP_WD_INITIAL0_OFS 0x0098 94 #define GIC_VP_COMPARE_LO_OFS 0x00a0 95 #define GIC_VP_COMPARE_HI_OFS 0x00a4 96 #define GIC_VL_BRK_GROUP 0x3080 97 98 /* User-Mode Visible Section Register */ 99 /* Read-only alias for GIC Shared CounterLo */ 100 #define GIC_USER_MODE_COUNTERLO 0x0000 101 /* Read-only alias for GIC Shared CounterHi */ 102 #define GIC_USER_MODE_COUNTERHI 0x0004 103 104 /* Masks */ 105 #define GIC_SH_CONFIG_COUNTSTOP_SHF 28 106 #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) 107 #define GIC_SH_CONFIG_COUNTBITS_SHF 24 108 #define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) 109 #define GIC_SH_CONFIG_NUMINTRS_SHF 16 110 #define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) 111 #define GIC_SH_CONFIG_PVPS_SHF 0 112 #define GIC_SH_CONFIG_PVPS_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPS_SHF) 113 114 #define GIC_SH_WEDGE_RW_SHF 31 115 #define GIC_SH_WEDGE_RW_MSK (MSK(1) << GIC_SH_WEDGE_RW_SHF) 116 117 #define GIC_MAP_TO_PIN_SHF 31 118 #define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) 119 #define GIC_MAP_TO_NMI_SHF 30 120 #define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) 121 #define GIC_MAP_TO_YQ_SHF 29 122 #define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) 123 #define GIC_MAP_SHF 0 124 #define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) 125 #define GIC_MAP_TO_PIN_REG_MSK \ 126 (GIC_MAP_TO_PIN_MSK | GIC_MAP_TO_NMI_MSK | GIC_MAP_TO_YQ_MSK | GIC_MAP_MSK) 127 128 /* GIC_VP_CTL Masks */ 129 #define GIC_VP_CTL_FDC_RTBL_SHF 4 130 #define GIC_VP_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VP_CTL_FDC_RTBL_SHF) 131 #define GIC_VP_CTL_SWINT_RTBL_SHF 3 132 #define GIC_VP_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VP_CTL_SWINT_RTBL_SHF) 133 #define GIC_VP_CTL_PERFCNT_RTBL_SHF 2 134 #define GIC_VP_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VP_CTL_PERFCNT_RTBL_SHF) 135 #define GIC_VP_CTL_TIMER_RTBL_SHF 1 136 #define GIC_VP_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VP_CTL_TIMER_RTBL_SHF) 137 #define GIC_VP_CTL_EIC_MODE_SHF 0 138 #define GIC_VP_CTL_EIC_MODE_MSK (MSK(1) << GIC_VP_CTL_EIC_MODE_SHF) 139 140 /* GIC_VP_MASK Masks */ 141 #define GIC_VP_MASK_FDC_SHF 6 142 #define GIC_VP_MASK_FDC_MSK (MSK(1) << GIC_VP_MASK_FDC_SHF) 143 #define GIC_VP_MASK_SWINT1_SHF 5 144 #define GIC_VP_MASK_SWINT1_MSK (MSK(1) << GIC_VP_MASK_SWINT1_SHF) 145 #define GIC_VP_MASK_SWINT0_SHF 4 146 #define GIC_VP_MASK_SWINT0_MSK (MSK(1) << GIC_VP_MASK_SWINT0_SHF) 147 #define GIC_VP_MASK_PERFCNT_SHF 3 148 #define GIC_VP_MASK_PERFCNT_MSK (MSK(1) << GIC_VP_MASK_PERFCNT_SHF) 149 #define GIC_VP_MASK_TIMER_SHF 2 150 #define GIC_VP_MASK_TIMER_MSK (MSK(1) << GIC_VP_MASK_TIMER_SHF) 151 #define GIC_VP_MASK_CMP_SHF 1 152 #define GIC_VP_MASK_CMP_MSK (MSK(1) << GIC_VP_MASK_CMP_SHF) 153 #define GIC_VP_MASK_WD_SHF 0 154 #define GIC_VP_MASK_WD_MSK (MSK(1) << GIC_VP_MASK_WD_SHF) 155 #define GIC_VP_SET_RESET_MSK (MSK(7) << GIC_VP_MASK_WD_SHF) 156 157 #define GIC_CPU_INT_MAX 5 /* Core Interrupt 7 */ 158 #define GIC_CPU_PIN_OFFSET 2 159 160 /* Local GIC interrupts. */ 161 #define GIC_NUM_LOCAL_INTRS 7 162 #define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */ 163 #define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */ 164 #define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */ 165 #define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */ 166 #define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */ 167 #define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */ 168 #define GIC_LOCAL_INT_WD 0 /* GIC watchdog */ 169 170 #define TYPE_MIPS_GIC "mips-gic" 171 #define MIPS_GIC(obj) OBJECT_CHECK(MIPSGICState, (obj), TYPE_MIPS_GIC) 172 173 /* Support up to 32 VPs and 256 IRQs */ 174 #define GIC_MAX_VPS 32 175 #define GIC_MAX_INTRS 256 176 177 typedef struct MIPSGICState MIPSGICState; 178 typedef struct MIPSGICIRQState MIPSGICIRQState; 179 typedef struct MIPSGICVPState MIPSGICVPState; 180 181 struct MIPSGICIRQState { 182 uint8_t enabled; 183 uint8_t pending; 184 uint32_t map_pin; 185 int32_t map_vp; 186 qemu_irq irq; 187 }; 188 189 struct MIPSGICVPState { 190 uint32_t ctl; 191 uint32_t pend; 192 uint32_t mask; 193 uint32_t compare_map; 194 uint32_t other_addr; 195 CPUMIPSState *env; 196 }; 197 198 struct MIPSGICState { 199 SysBusDevice parent_obj; 200 MemoryRegion mr; 201 202 /* Shared Section Registers */ 203 uint32_t sh_config; 204 MIPSGICIRQState *irq_state; 205 206 /* VP Local/Other Section Registers */ 207 MIPSGICVPState *vps; 208 209 /* GIC VP Timer */ 210 MIPSGICTimerState *gic_timer; 211 212 int32_t num_vps; 213 int32_t num_irq; 214 }; 215 216 #endif /* MIPS_GIC_H */ 217