1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 7 * Copyright (C) 2016 Imagination Technologies 8 * 9 */ 10 11 #ifndef MIPS_GIC_H 12 #define MIPS_GIC_H 13 14 #include "qemu/units.h" 15 #include "hw/timer/mips_gictimer.h" 16 #include "cpu.h" 17 /* 18 * GIC Specific definitions 19 */ 20 21 /* The MIPS default location */ 22 #define GIC_BASE_ADDR 0x1bdc0000ULL 23 #define GIC_ADDRSPACE_SZ (128 * KiB) 24 25 /* Constants */ 26 #define GIC_POL_POS 1 27 #define GIC_POL_NEG 0 28 #define GIC_TRIG_EDGE 1 29 #define GIC_TRIG_LEVEL 0 30 31 #define MSK(n) ((1ULL << (n)) - 1) 32 33 /* GIC Address Space */ 34 #define SHARED_SECTION_OFS 0x0000 35 #define SHARED_SECTION_SIZE 0x8000 36 #define VP_LOCAL_SECTION_OFS 0x8000 37 #define VP_LOCAL_SECTION_SIZE 0x4000 38 #define VP_OTHER_SECTION_OFS 0xc000 39 #define VP_OTHER_SECTION_SIZE 0x4000 40 #define USM_VISIBLE_SECTION_OFS 0x10000 41 #define USM_VISIBLE_SECTION_SIZE 0x10000 42 43 /* Register Map for Shared Section */ 44 45 #define GIC_SH_CONFIG_OFS 0x0000 46 47 /* Shared Global Counter */ 48 #define GIC_SH_COUNTERLO_OFS 0x0010 49 #define GIC_SH_COUNTERHI_OFS 0x0014 50 #define GIC_SH_REVISIONID_OFS 0x0020 51 52 /* Set/Clear corresponding bit in Edge Detect Register */ 53 #define GIC_SH_WEDGE_OFS 0x0280 54 55 /* Reset Mask - Disables Interrupt */ 56 #define GIC_SH_RMASK_OFS 0x0300 57 #define GIC_SH_RMASK_LAST_OFS 0x031c 58 59 /* Set Mask (WO) - Enables Interrupt */ 60 #define GIC_SH_SMASK_OFS 0x0380 61 #define GIC_SH_SMASK_LAST_OFS 0x039c 62 63 /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ 64 #define GIC_SH_MASK_OFS 0x0400 65 #define GIC_SH_MASK_LAST_OFS 0x041c 66 67 /* Pending Global Interrupts (RO) */ 68 #define GIC_SH_PEND_OFS 0x0480 69 #define GIC_SH_PEND_LAST_OFS 0x049c 70 71 #define GIC_SH_MAP0_PIN_OFS 0x0500 72 #define GIC_SH_MAP255_PIN_OFS 0x08fc 73 74 #define GIC_SH_MAP0_VP_OFS 0x2000 75 #define GIC_SH_MAP255_VP_LAST_OFS 0x3fe4 76 77 /* Register Map for Local Section */ 78 #define GIC_VP_CTL_OFS 0x0000 79 #define GIC_VP_PEND_OFS 0x0004 80 #define GIC_VP_MASK_OFS 0x0008 81 #define GIC_VP_RMASK_OFS 0x000c 82 #define GIC_VP_SMASK_OFS 0x0010 83 #define GIC_VP_WD_MAP_OFS 0x0040 84 #define GIC_VP_COMPARE_MAP_OFS 0x0044 85 #define GIC_VP_TIMER_MAP_OFS 0x0048 86 #define GIC_VP_FDC_MAP_OFS 0x004c 87 #define GIC_VP_PERFCTR_MAP_OFS 0x0050 88 #define GIC_VP_SWINT0_MAP_OFS 0x0054 89 #define GIC_VP_SWINT1_MAP_OFS 0x0058 90 #define GIC_VP_OTHER_ADDR_OFS 0x0080 91 #define GIC_VP_IDENT_OFS 0x0088 92 #define GIC_VP_WD_CONFIG0_OFS 0x0090 93 #define GIC_VP_WD_COUNT0_OFS 0x0094 94 #define GIC_VP_WD_INITIAL0_OFS 0x0098 95 #define GIC_VP_COMPARE_LO_OFS 0x00a0 96 #define GIC_VP_COMPARE_HI_OFS 0x00a4 97 #define GIC_VL_BRK_GROUP 0x3080 98 99 /* User-Mode Visible Section Register */ 100 /* Read-only alias for GIC Shared CounterLo */ 101 #define GIC_USER_MODE_COUNTERLO 0x0000 102 /* Read-only alias for GIC Shared CounterHi */ 103 #define GIC_USER_MODE_COUNTERHI 0x0004 104 105 /* Masks */ 106 #define GIC_SH_CONFIG_COUNTSTOP_SHF 28 107 #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) 108 #define GIC_SH_CONFIG_COUNTBITS_SHF 24 109 #define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) 110 #define GIC_SH_CONFIG_NUMINTRS_SHF 16 111 #define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) 112 #define GIC_SH_CONFIG_PVPS_SHF 0 113 #define GIC_SH_CONFIG_PVPS_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPS_SHF) 114 115 #define GIC_SH_WEDGE_RW_SHF 31 116 #define GIC_SH_WEDGE_RW_MSK (MSK(1) << GIC_SH_WEDGE_RW_SHF) 117 118 #define GIC_MAP_TO_PIN_SHF 31 119 #define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) 120 #define GIC_MAP_TO_NMI_SHF 30 121 #define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) 122 #define GIC_MAP_TO_YQ_SHF 29 123 #define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) 124 #define GIC_MAP_SHF 0 125 #define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) 126 #define GIC_MAP_TO_PIN_REG_MSK \ 127 (GIC_MAP_TO_PIN_MSK | GIC_MAP_TO_NMI_MSK | GIC_MAP_TO_YQ_MSK | GIC_MAP_MSK) 128 129 /* GIC_VP_CTL Masks */ 130 #define GIC_VP_CTL_FDC_RTBL_SHF 4 131 #define GIC_VP_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VP_CTL_FDC_RTBL_SHF) 132 #define GIC_VP_CTL_SWINT_RTBL_SHF 3 133 #define GIC_VP_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VP_CTL_SWINT_RTBL_SHF) 134 #define GIC_VP_CTL_PERFCNT_RTBL_SHF 2 135 #define GIC_VP_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VP_CTL_PERFCNT_RTBL_SHF) 136 #define GIC_VP_CTL_TIMER_RTBL_SHF 1 137 #define GIC_VP_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VP_CTL_TIMER_RTBL_SHF) 138 #define GIC_VP_CTL_EIC_MODE_SHF 0 139 #define GIC_VP_CTL_EIC_MODE_MSK (MSK(1) << GIC_VP_CTL_EIC_MODE_SHF) 140 141 /* GIC_VP_MASK Masks */ 142 #define GIC_VP_MASK_FDC_SHF 6 143 #define GIC_VP_MASK_FDC_MSK (MSK(1) << GIC_VP_MASK_FDC_SHF) 144 #define GIC_VP_MASK_SWINT1_SHF 5 145 #define GIC_VP_MASK_SWINT1_MSK (MSK(1) << GIC_VP_MASK_SWINT1_SHF) 146 #define GIC_VP_MASK_SWINT0_SHF 4 147 #define GIC_VP_MASK_SWINT0_MSK (MSK(1) << GIC_VP_MASK_SWINT0_SHF) 148 #define GIC_VP_MASK_PERFCNT_SHF 3 149 #define GIC_VP_MASK_PERFCNT_MSK (MSK(1) << GIC_VP_MASK_PERFCNT_SHF) 150 #define GIC_VP_MASK_TIMER_SHF 2 151 #define GIC_VP_MASK_TIMER_MSK (MSK(1) << GIC_VP_MASK_TIMER_SHF) 152 #define GIC_VP_MASK_CMP_SHF 1 153 #define GIC_VP_MASK_CMP_MSK (MSK(1) << GIC_VP_MASK_CMP_SHF) 154 #define GIC_VP_MASK_WD_SHF 0 155 #define GIC_VP_MASK_WD_MSK (MSK(1) << GIC_VP_MASK_WD_SHF) 156 #define GIC_VP_SET_RESET_MSK (MSK(7) << GIC_VP_MASK_WD_SHF) 157 158 #define GIC_CPU_INT_MAX 5 /* Core Interrupt 7 */ 159 #define GIC_CPU_PIN_OFFSET 2 160 161 /* Local GIC interrupts. */ 162 #define GIC_NUM_LOCAL_INTRS 7 163 #define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */ 164 #define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */ 165 #define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */ 166 #define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */ 167 #define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */ 168 #define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */ 169 #define GIC_LOCAL_INT_WD 0 /* GIC watchdog */ 170 171 #define TYPE_MIPS_GIC "mips-gic" 172 #define MIPS_GIC(obj) OBJECT_CHECK(MIPSGICState, (obj), TYPE_MIPS_GIC) 173 174 /* Support up to 32 VPs and 256 IRQs */ 175 #define GIC_MAX_VPS 32 176 #define GIC_MAX_INTRS 256 177 178 typedef struct MIPSGICState MIPSGICState; 179 typedef struct MIPSGICIRQState MIPSGICIRQState; 180 typedef struct MIPSGICVPState MIPSGICVPState; 181 182 struct MIPSGICIRQState { 183 uint8_t enabled; 184 uint8_t pending; 185 uint32_t map_pin; 186 int32_t map_vp; 187 qemu_irq irq; 188 }; 189 190 struct MIPSGICVPState { 191 uint32_t ctl; 192 uint32_t pend; 193 uint32_t mask; 194 uint32_t compare_map; 195 uint32_t other_addr; 196 CPUMIPSState *env; 197 }; 198 199 struct MIPSGICState { 200 SysBusDevice parent_obj; 201 MemoryRegion mr; 202 203 /* Shared Section Registers */ 204 uint32_t sh_config; 205 MIPSGICIRQState *irq_state; 206 207 /* VP Local/Other Section Registers */ 208 MIPSGICVPState *vps; 209 210 /* GIC VP Timer */ 211 MIPSGICTimerState *gic_timer; 212 213 int32_t num_vps; 214 int32_t num_irq; 215 }; 216 217 #endif /* MIPS_GIC_H */ 218