1e8bd336dSYongbok Kim /* 2e8bd336dSYongbok Kim * This file is subject to the terms and conditions of the GNU General Public 3e8bd336dSYongbok Kim * License. See the file "COPYING" in the main directory of this archive 4e8bd336dSYongbok Kim * for more details. 5e8bd336dSYongbok Kim * 6e8bd336dSYongbok Kim * Copyright (C) 2000, 07 MIPS Technologies, Inc. 7e8bd336dSYongbok Kim * Copyright (C) 2016 Imagination Technologies 8e8bd336dSYongbok Kim * 9e8bd336dSYongbok Kim */ 10e8bd336dSYongbok Kim 11*2a6a4076SMarkus Armbruster #ifndef MIPS_GIC_H 12*2a6a4076SMarkus Armbruster #define MIPS_GIC_H 13e8bd336dSYongbok Kim 14e8bd336dSYongbok Kim #include "hw/timer/mips_gictimer.h" 15e8bd336dSYongbok Kim #include "cpu.h" 16e8bd336dSYongbok Kim /* 17e8bd336dSYongbok Kim * GIC Specific definitions 18e8bd336dSYongbok Kim */ 19e8bd336dSYongbok Kim 20e8bd336dSYongbok Kim /* The MIPS default location */ 21e8bd336dSYongbok Kim #define GIC_BASE_ADDR 0x1bdc0000ULL 22e8bd336dSYongbok Kim #define GIC_ADDRSPACE_SZ (128 * 1024) 23e8bd336dSYongbok Kim 24e8bd336dSYongbok Kim /* Constants */ 25e8bd336dSYongbok Kim #define GIC_POL_POS 1 26e8bd336dSYongbok Kim #define GIC_POL_NEG 0 27e8bd336dSYongbok Kim #define GIC_TRIG_EDGE 1 28e8bd336dSYongbok Kim #define GIC_TRIG_LEVEL 0 29e8bd336dSYongbok Kim 30e8bd336dSYongbok Kim #define MSK(n) ((1ULL << (n)) - 1) 31e8bd336dSYongbok Kim 32e8bd336dSYongbok Kim /* GIC Address Space */ 33e8bd336dSYongbok Kim #define SHARED_SECTION_OFS 0x0000 34e8bd336dSYongbok Kim #define SHARED_SECTION_SIZE 0x8000 35e8bd336dSYongbok Kim #define VP_LOCAL_SECTION_OFS 0x8000 36e8bd336dSYongbok Kim #define VP_LOCAL_SECTION_SIZE 0x4000 37e8bd336dSYongbok Kim #define VP_OTHER_SECTION_OFS 0xc000 38e8bd336dSYongbok Kim #define VP_OTHER_SECTION_SIZE 0x4000 39e8bd336dSYongbok Kim #define USM_VISIBLE_SECTION_OFS 0x10000 40e8bd336dSYongbok Kim #define USM_VISIBLE_SECTION_SIZE 0x10000 41e8bd336dSYongbok Kim 42e8bd336dSYongbok Kim /* Register Map for Shared Section */ 43e8bd336dSYongbok Kim 44e8bd336dSYongbok Kim #define GIC_SH_CONFIG_OFS 0x0000 45e8bd336dSYongbok Kim 46e8bd336dSYongbok Kim /* Shared Global Counter */ 47e8bd336dSYongbok Kim #define GIC_SH_COUNTERLO_OFS 0x0010 48e8bd336dSYongbok Kim #define GIC_SH_COUNTERHI_OFS 0x0014 49e8bd336dSYongbok Kim #define GIC_SH_REVISIONID_OFS 0x0020 50e8bd336dSYongbok Kim 51e8bd336dSYongbok Kim /* Set/Clear corresponding bit in Edge Detect Register */ 52e8bd336dSYongbok Kim #define GIC_SH_WEDGE_OFS 0x0280 53e8bd336dSYongbok Kim 54e8bd336dSYongbok Kim /* Reset Mask - Disables Interrupt */ 55e8bd336dSYongbok Kim #define GIC_SH_RMASK_OFS 0x0300 56e8bd336dSYongbok Kim #define GIC_SH_RMASK_LAST_OFS 0x031c 57e8bd336dSYongbok Kim 58e8bd336dSYongbok Kim /* Set Mask (WO) - Enables Interrupt */ 59e8bd336dSYongbok Kim #define GIC_SH_SMASK_OFS 0x0380 60e8bd336dSYongbok Kim #define GIC_SH_SMASK_LAST_OFS 0x039c 61e8bd336dSYongbok Kim 62e8bd336dSYongbok Kim /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ 63e8bd336dSYongbok Kim #define GIC_SH_MASK_OFS 0x0400 64e8bd336dSYongbok Kim #define GIC_SH_MASK_LAST_OFS 0x041c 65e8bd336dSYongbok Kim 66e8bd336dSYongbok Kim /* Pending Global Interrupts (RO) */ 67e8bd336dSYongbok Kim #define GIC_SH_PEND_OFS 0x0480 68e8bd336dSYongbok Kim #define GIC_SH_PEND_LAST_OFS 0x049c 69e8bd336dSYongbok Kim 70e8bd336dSYongbok Kim #define GIC_SH_MAP0_PIN_OFS 0x0500 71e8bd336dSYongbok Kim #define GIC_SH_MAP255_PIN_OFS 0x08fc 72e8bd336dSYongbok Kim 73e8bd336dSYongbok Kim #define GIC_SH_MAP0_VP_OFS 0x2000 74e8bd336dSYongbok Kim #define GIC_SH_MAP255_VP_LAST_OFS 0x3fe4 75e8bd336dSYongbok Kim 76e8bd336dSYongbok Kim /* Register Map for Local Section */ 77e8bd336dSYongbok Kim #define GIC_VP_CTL_OFS 0x0000 78e8bd336dSYongbok Kim #define GIC_VP_PEND_OFS 0x0004 79e8bd336dSYongbok Kim #define GIC_VP_MASK_OFS 0x0008 80e8bd336dSYongbok Kim #define GIC_VP_RMASK_OFS 0x000c 81e8bd336dSYongbok Kim #define GIC_VP_SMASK_OFS 0x0010 82e8bd336dSYongbok Kim #define GIC_VP_WD_MAP_OFS 0x0040 83e8bd336dSYongbok Kim #define GIC_VP_COMPARE_MAP_OFS 0x0044 84e8bd336dSYongbok Kim #define GIC_VP_TIMER_MAP_OFS 0x0048 85e8bd336dSYongbok Kim #define GIC_VP_FDC_MAP_OFS 0x004c 86e8bd336dSYongbok Kim #define GIC_VP_PERFCTR_MAP_OFS 0x0050 87e8bd336dSYongbok Kim #define GIC_VP_SWINT0_MAP_OFS 0x0054 88e8bd336dSYongbok Kim #define GIC_VP_SWINT1_MAP_OFS 0x0058 89e8bd336dSYongbok Kim #define GIC_VP_OTHER_ADDR_OFS 0x0080 90e8bd336dSYongbok Kim #define GIC_VP_IDENT_OFS 0x0088 91e8bd336dSYongbok Kim #define GIC_VP_WD_CONFIG0_OFS 0x0090 92e8bd336dSYongbok Kim #define GIC_VP_WD_COUNT0_OFS 0x0094 93e8bd336dSYongbok Kim #define GIC_VP_WD_INITIAL0_OFS 0x0098 94e8bd336dSYongbok Kim #define GIC_VP_COMPARE_LO_OFS 0x00a0 95e8bd336dSYongbok Kim #define GIC_VP_COMPARE_HI_OFS 0x00a4 96e8bd336dSYongbok Kim #define GIC_VL_BRK_GROUP 0x3080 97e8bd336dSYongbok Kim 98e8bd336dSYongbok Kim /* User-Mode Visible Section Register */ 99e8bd336dSYongbok Kim /* Read-only alias for GIC Shared CounterLo */ 100e8bd336dSYongbok Kim #define GIC_USER_MODE_COUNTERLO 0x0000 101e8bd336dSYongbok Kim /* Read-only alias for GIC Shared CounterHi */ 102e8bd336dSYongbok Kim #define GIC_USER_MODE_COUNTERHI 0x0004 103e8bd336dSYongbok Kim 104e8bd336dSYongbok Kim /* Masks */ 105e8bd336dSYongbok Kim #define GIC_SH_CONFIG_COUNTSTOP_SHF 28 106e8bd336dSYongbok Kim #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) 107e8bd336dSYongbok Kim #define GIC_SH_CONFIG_COUNTBITS_SHF 24 108e8bd336dSYongbok Kim #define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) 109e8bd336dSYongbok Kim #define GIC_SH_CONFIG_NUMINTRS_SHF 16 110e8bd336dSYongbok Kim #define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) 111e8bd336dSYongbok Kim #define GIC_SH_CONFIG_PVPS_SHF 0 112e8bd336dSYongbok Kim #define GIC_SH_CONFIG_PVPS_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPS_SHF) 113e8bd336dSYongbok Kim 114e8bd336dSYongbok Kim #define GIC_SH_WEDGE_RW_SHF 31 115e8bd336dSYongbok Kim #define GIC_SH_WEDGE_RW_MSK (MSK(1) << GIC_SH_WEDGE_RW_SHF) 116e8bd336dSYongbok Kim 117e8bd336dSYongbok Kim #define GIC_MAP_TO_PIN_SHF 31 118e8bd336dSYongbok Kim #define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) 119e8bd336dSYongbok Kim #define GIC_MAP_TO_NMI_SHF 30 120e8bd336dSYongbok Kim #define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) 121e8bd336dSYongbok Kim #define GIC_MAP_TO_YQ_SHF 29 122e8bd336dSYongbok Kim #define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) 123e8bd336dSYongbok Kim #define GIC_MAP_SHF 0 124e8bd336dSYongbok Kim #define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) 125e8bd336dSYongbok Kim #define GIC_MAP_TO_PIN_REG_MSK \ 126e8bd336dSYongbok Kim (GIC_MAP_TO_PIN_MSK | GIC_MAP_TO_NMI_MSK | GIC_MAP_TO_YQ_MSK | GIC_MAP_MSK) 127e8bd336dSYongbok Kim 128e8bd336dSYongbok Kim /* GIC_VP_CTL Masks */ 129e8bd336dSYongbok Kim #define GIC_VP_CTL_FDC_RTBL_SHF 4 130e8bd336dSYongbok Kim #define GIC_VP_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VP_CTL_FDC_RTBL_SHF) 131e8bd336dSYongbok Kim #define GIC_VP_CTL_SWINT_RTBL_SHF 3 132e8bd336dSYongbok Kim #define GIC_VP_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VP_CTL_SWINT_RTBL_SHF) 133e8bd336dSYongbok Kim #define GIC_VP_CTL_PERFCNT_RTBL_SHF 2 134e8bd336dSYongbok Kim #define GIC_VP_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VP_CTL_PERFCNT_RTBL_SHF) 135e8bd336dSYongbok Kim #define GIC_VP_CTL_TIMER_RTBL_SHF 1 136e8bd336dSYongbok Kim #define GIC_VP_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VP_CTL_TIMER_RTBL_SHF) 137e8bd336dSYongbok Kim #define GIC_VP_CTL_EIC_MODE_SHF 0 138e8bd336dSYongbok Kim #define GIC_VP_CTL_EIC_MODE_MSK (MSK(1) << GIC_VP_CTL_EIC_MODE_SHF) 139e8bd336dSYongbok Kim 140e8bd336dSYongbok Kim /* GIC_VP_MASK Masks */ 141e8bd336dSYongbok Kim #define GIC_VP_MASK_FDC_SHF 6 142e8bd336dSYongbok Kim #define GIC_VP_MASK_FDC_MSK (MSK(1) << GIC_VP_MASK_FDC_SHF) 143e8bd336dSYongbok Kim #define GIC_VP_MASK_SWINT1_SHF 5 144e8bd336dSYongbok Kim #define GIC_VP_MASK_SWINT1_MSK (MSK(1) << GIC_VP_MASK_SWINT1_SHF) 145e8bd336dSYongbok Kim #define GIC_VP_MASK_SWINT0_SHF 4 146e8bd336dSYongbok Kim #define GIC_VP_MASK_SWINT0_MSK (MSK(1) << GIC_VP_MASK_SWINT0_SHF) 147e8bd336dSYongbok Kim #define GIC_VP_MASK_PERFCNT_SHF 3 148e8bd336dSYongbok Kim #define GIC_VP_MASK_PERFCNT_MSK (MSK(1) << GIC_VP_MASK_PERFCNT_SHF) 149e8bd336dSYongbok Kim #define GIC_VP_MASK_TIMER_SHF 2 150e8bd336dSYongbok Kim #define GIC_VP_MASK_TIMER_MSK (MSK(1) << GIC_VP_MASK_TIMER_SHF) 151e8bd336dSYongbok Kim #define GIC_VP_MASK_CMP_SHF 1 152e8bd336dSYongbok Kim #define GIC_VP_MASK_CMP_MSK (MSK(1) << GIC_VP_MASK_CMP_SHF) 153e8bd336dSYongbok Kim #define GIC_VP_MASK_WD_SHF 0 154e8bd336dSYongbok Kim #define GIC_VP_MASK_WD_MSK (MSK(1) << GIC_VP_MASK_WD_SHF) 155e8bd336dSYongbok Kim #define GIC_VP_SET_RESET_MSK (MSK(7) << GIC_VP_MASK_WD_SHF) 156e8bd336dSYongbok Kim 157e8bd336dSYongbok Kim #define GIC_CPU_INT_MAX 5 /* Core Interrupt 7 */ 158e8bd336dSYongbok Kim #define GIC_CPU_PIN_OFFSET 2 159e8bd336dSYongbok Kim 160e8bd336dSYongbok Kim /* Local GIC interrupts. */ 161e8bd336dSYongbok Kim #define GIC_NUM_LOCAL_INTRS 7 162e8bd336dSYongbok Kim #define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */ 163e8bd336dSYongbok Kim #define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */ 164e8bd336dSYongbok Kim #define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */ 165e8bd336dSYongbok Kim #define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */ 166e8bd336dSYongbok Kim #define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */ 167e8bd336dSYongbok Kim #define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */ 168e8bd336dSYongbok Kim #define GIC_LOCAL_INT_WD 0 /* GIC watchdog */ 169e8bd336dSYongbok Kim 170e8bd336dSYongbok Kim #define TYPE_MIPS_GIC "mips-gic" 171e8bd336dSYongbok Kim #define MIPS_GIC(obj) OBJECT_CHECK(MIPSGICState, (obj), TYPE_MIPS_GIC) 172e8bd336dSYongbok Kim 173e8bd336dSYongbok Kim /* Support up to 32 VPs and 256 IRQs */ 174e8bd336dSYongbok Kim #define GIC_MAX_VPS 32 175e8bd336dSYongbok Kim #define GIC_MAX_INTRS 256 176e8bd336dSYongbok Kim 177e8bd336dSYongbok Kim typedef struct MIPSGICState MIPSGICState; 178e8bd336dSYongbok Kim typedef struct MIPSGICIRQState MIPSGICIRQState; 179e8bd336dSYongbok Kim typedef struct MIPSGICVPState MIPSGICVPState; 180e8bd336dSYongbok Kim 181e8bd336dSYongbok Kim struct MIPSGICIRQState { 182e8bd336dSYongbok Kim uint8_t enabled; 183e8bd336dSYongbok Kim uint8_t pending; 184e8bd336dSYongbok Kim uint32_t map_pin; 185e8bd336dSYongbok Kim int32_t map_vp; 186e8bd336dSYongbok Kim qemu_irq irq; 187e8bd336dSYongbok Kim }; 188e8bd336dSYongbok Kim 189e8bd336dSYongbok Kim struct MIPSGICVPState { 190e8bd336dSYongbok Kim uint32_t ctl; 191e8bd336dSYongbok Kim uint32_t pend; 192e8bd336dSYongbok Kim uint32_t mask; 193e8bd336dSYongbok Kim uint32_t compare_map; 194e8bd336dSYongbok Kim uint32_t other_addr; 195e8bd336dSYongbok Kim CPUMIPSState *env; 196e8bd336dSYongbok Kim }; 197e8bd336dSYongbok Kim 198e8bd336dSYongbok Kim struct MIPSGICState { 199e8bd336dSYongbok Kim SysBusDevice parent_obj; 200e8bd336dSYongbok Kim MemoryRegion mr; 201e8bd336dSYongbok Kim 202e8bd336dSYongbok Kim /* Shared Section Registers */ 203e8bd336dSYongbok Kim uint32_t sh_config; 204e8bd336dSYongbok Kim MIPSGICIRQState *irq_state; 205e8bd336dSYongbok Kim 206e8bd336dSYongbok Kim /* VP Local/Other Section Registers */ 207e8bd336dSYongbok Kim MIPSGICVPState *vps; 208e8bd336dSYongbok Kim 209e8bd336dSYongbok Kim /* GIC VP Timer */ 210e8bd336dSYongbok Kim MIPSGICTimerState *gic_timer; 211e8bd336dSYongbok Kim 212e8bd336dSYongbok Kim int32_t num_vps; 213e8bd336dSYongbok Kim int32_t num_irq; 214e8bd336dSYongbok Kim }; 215e8bd336dSYongbok Kim 216*2a6a4076SMarkus Armbruster #endif /* MIPS_GIC_H */ 217