xref: /openbmc/qemu/include/hw/intc/loongson_ipi_common.h (revision a022e0de53579da9df20945de70a82957258a972)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Loongson ipi interrupt header files
4  *
5  * Copyright (C) 2021 Loongson Technology Corporation Limited
6  */
7 
8 #ifndef HW_LOONGSON_IPI_COMMON_H
9 #define HW_LOONGSON_IPI_COMMON_H
10 
11 #include "qom/object.h"
12 #include "hw/sysbus.h"
13 
14 #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common"
15 OBJECT_DECLARE_TYPE(LoongsonIPICommonState,
16                     LoongsonIPICommonClass, LOONGSON_IPI_COMMON)
17 
18 struct LoongsonIPICommonState {
19     SysBusDevice parent_obj;
20 };
21 
22 struct LoongsonIPICommonClass {
23     SysBusDeviceClass parent_class;
24 };
25 
26 /* Mainy used by iocsr read and write */
27 #define SMP_IPI_MAILBOX         0x1000ULL
28 
29 #define CORE_STATUS_OFF         0x0
30 #define CORE_EN_OFF             0x4
31 #define CORE_SET_OFF            0x8
32 #define CORE_CLEAR_OFF          0xc
33 #define CORE_BUF_20             0x20
34 #define CORE_BUF_28             0x28
35 #define CORE_BUF_30             0x30
36 #define CORE_BUF_38             0x38
37 #define IOCSR_IPI_SEND          0x40
38 #define IOCSR_MAIL_SEND         0x48
39 #define IOCSR_ANY_SEND          0x158
40 
41 #define MAIL_SEND_ADDR          (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
42 #define MAIL_SEND_OFFSET        0
43 #define ANY_SEND_OFFSET         (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
44 
45 #endif
46