1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Loongson ipi interrupt header files 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef HW_LOONGSON_IPI_H 9 #define HW_LOONGSON_IPI_H 10 11 #include "qom/object.h" 12 #include "hw/intc/loongson_ipi_common.h" 13 #include "hw/sysbus.h" 14 15 /* Mainy used by iocsr read and write */ 16 #define SMP_IPI_MAILBOX 0x1000ULL 17 #define CORE_STATUS_OFF 0x0 18 #define CORE_EN_OFF 0x4 19 #define CORE_SET_OFF 0x8 20 #define CORE_CLEAR_OFF 0xc 21 #define CORE_BUF_20 0x20 22 #define CORE_BUF_28 0x28 23 #define CORE_BUF_30 0x30 24 #define CORE_BUF_38 0x38 25 #define IOCSR_IPI_SEND 0x40 26 #define IOCSR_MAIL_SEND 0x48 27 #define IOCSR_ANY_SEND 0x158 28 29 #define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) 30 #define MAIL_SEND_OFFSET 0 31 #define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) 32 33 #define IPI_MBX_NUM 4 34 35 #define TYPE_LOONGSON_IPI "loongson_ipi" 36 OBJECT_DECLARE_TYPE(LoongsonIPIState, LoongsonIPIClass, LOONGSON_IPI) 37 38 typedef struct IPICore { 39 LoongsonIPIState *ipi; 40 MemoryRegion *ipi_mmio_mem; 41 uint32_t status; 42 uint32_t en; 43 uint32_t set; 44 uint32_t clear; 45 /* 64bit buf divide into 2 32bit buf */ 46 uint32_t buf[IPI_MBX_NUM * 2]; 47 qemu_irq irq; 48 } IPICore; 49 50 struct LoongsonIPIClass { 51 LoongsonIPICommonClass parent_class; 52 53 DeviceRealize parent_realize; 54 DeviceUnrealize parent_unrealize; 55 }; 56 57 struct LoongsonIPIState { 58 LoongsonIPICommonState parent_obj; 59 60 MemoryRegion ipi_iocsr_mem; 61 MemoryRegion ipi64_iocsr_mem; 62 uint32_t num_cpu; 63 IPICore *cpu; 64 }; 65 66 #endif 67