1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch 7A1000 I/O interrupt controller definitions 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef HW_LOONGARCH_PCH_PIC_H 9 #define HW_LOONGARCH_PCH_PIC_H 10 11 #include "hw/intc/loongarch_pic_common.h" 12 13 #define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic" 14 #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name 15 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC) 16 17 struct LoongArchPCHPIC { 18 SysBusDevice parent_obj; 19 qemu_irq parent_irq[64]; 20 uint64_t int_mask; /*0x020 interrupt mask register*/ 21 uint64_t htmsi_en; /*0x040 1=msi*/ 22 uint64_t intedge; /*0x060 edge=1 level =0*/ 23 uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/ 24 uint64_t auto_crtl0; /*0x0c0*/ 25 uint64_t auto_crtl1; /*0x0e0*/ 26 uint64_t last_intirr; /* edge detection */ 27 uint64_t intirr; /* 0x380 interrupt request register */ 28 uint64_t intisr; /* 0x3a0 interrupt service register */ 29 /* 30 * 0x3e0 interrupt level polarity selection 31 * register 0 for high level trigger 32 */ 33 uint64_t int_polarity; 34 35 uint8_t route_entry[64]; /*0x100 - 0x138*/ 36 uint8_t htmsi_vector[64]; /*0x200 - 0x238*/ 37 38 MemoryRegion iomem32_low; 39 MemoryRegion iomem32_high; 40 MemoryRegion iomem8; 41 unsigned int irq_num; 42 }; 43 #endif /* HW_LOONGARCH_PCH_PIC_H */ 44