1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * LoongArch 7A1000 I/O interrupt controller definitions
4  *
5  * Copyright (c) 2021 Loongson Technology Corporation Limited
6  */
7 
8 #define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
9 #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
10 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
11 
12 #define PCH_PIC_IRQ_START               0
13 #define PCH_PIC_IRQ_END                 63
14 #define PCH_PIC_IRQ_NUM                 64
15 #define PCH_PIC_INT_ID_VAL              0x7000000UL
16 #define PCH_PIC_INT_ID_NUM              0x3f0001UL
17 
18 #define PCH_PIC_INT_ID_LO               0x00
19 #define PCH_PIC_INT_ID_HI               0x04
20 #define PCH_PIC_INT_MASK_LO             0x20
21 #define PCH_PIC_INT_MASK_HI             0x24
22 #define PCH_PIC_HTMSI_EN_LO             0x40
23 #define PCH_PIC_HTMSI_EN_HI             0x44
24 #define PCH_PIC_INT_EDGE_LO             0x60
25 #define PCH_PIC_INT_EDGE_HI             0x64
26 #define PCH_PIC_INT_CLEAR_LO            0x80
27 #define PCH_PIC_INT_CLEAR_HI            0x84
28 #define PCH_PIC_AUTO_CTRL0_LO           0xc0
29 #define PCH_PIC_AUTO_CTRL0_HI           0xc4
30 #define PCH_PIC_AUTO_CTRL1_LO           0xe0
31 #define PCH_PIC_AUTO_CTRL1_HI           0xe4
32 #define PCH_PIC_ROUTE_ENTRY_OFFSET      0x100
33 #define PCH_PIC_ROUTE_ENTRY_END         0x13f
34 #define PCH_PIC_HTMSI_VEC_OFFSET        0x200
35 #define PCH_PIC_HTMSI_VEC_END           0x23f
36 #define PCH_PIC_INT_STATUS_LO           0x3a0
37 #define PCH_PIC_INT_STATUS_HI           0x3a4
38 #define PCH_PIC_INT_POL_LO              0x3e0
39 #define PCH_PIC_INT_POL_HI              0x3e4
40 
41 #define STATUS_LO_START                 0
42 #define STATUS_HI_START                 0x4
43 #define POL_LO_START                    0x40
44 #define POL_HI_START                    0x44
45 struct LoongArchPCHPIC {
46     SysBusDevice parent_obj;
47     qemu_irq parent_irq[64];
48     uint64_t int_mask; /*0x020 interrupt mask register*/
49     uint64_t htmsi_en; /*0x040 1=msi*/
50     uint64_t intedge; /*0x060 edge=1 level  =0*/
51     uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
52     uint64_t auto_crtl0; /*0x0c0*/
53     uint64_t auto_crtl1; /*0x0e0*/
54     uint64_t last_intirr;    /* edge detection */
55     uint64_t intirr; /* 0x380 interrupt request register */
56     uint64_t intisr; /* 0x3a0 interrupt service register */
57     /*
58      * 0x3e0 interrupt level polarity selection
59      * register 0 for high level trigger
60      */
61     uint64_t int_polarity;
62 
63     uint8_t route_entry[64]; /*0x100 - 0x138*/
64     uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
65 
66     MemoryRegion iomem32_low;
67     MemoryRegion iomem32_high;
68     MemoryRegion iomem8;
69 };
70