1249ad85aSXiaojuan Yang /* SPDX-License-Identifier: GPL-2.0-or-later */
2249ad85aSXiaojuan Yang /*
3249ad85aSXiaojuan Yang  * LoongArch 7A1000 I/O interrupt controller definitions
4249ad85aSXiaojuan Yang  *
5249ad85aSXiaojuan Yang  * Copyright (C) 2021 Loongson Technology Corporation Limited
6249ad85aSXiaojuan Yang  */
7249ad85aSXiaojuan Yang 
8249ad85aSXiaojuan Yang #define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
9249ad85aSXiaojuan Yang OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
10249ad85aSXiaojuan Yang 
11249ad85aSXiaojuan Yang /* Msi irq start start from 64 to 255 */
12249ad85aSXiaojuan Yang #define PCH_MSI_IRQ_START   64
13249ad85aSXiaojuan Yang #define PCH_MSI_IRQ_END     255
14249ad85aSXiaojuan Yang #define PCH_MSI_IRQ_NUM     192
15249ad85aSXiaojuan Yang 
16249ad85aSXiaojuan Yang struct LoongArchPCHMSI {
17249ad85aSXiaojuan Yang     SysBusDevice parent_obj;
18249ad85aSXiaojuan Yang     qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
19249ad85aSXiaojuan Yang     MemoryRegion msi_mmio;
20*490c03abSMao Bibo     /* irq base passed to upper extioi intc */
21*490c03abSMao Bibo     unsigned int irq_base;
22249ad85aSXiaojuan Yang };
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