1*249ad85aSXiaojuan Yang /* SPDX-License-Identifier: GPL-2.0-or-later */
2*249ad85aSXiaojuan Yang /*
3*249ad85aSXiaojuan Yang  * LoongArch 7A1000 I/O interrupt controller definitions
4*249ad85aSXiaojuan Yang  *
5*249ad85aSXiaojuan Yang  * Copyright (C) 2021 Loongson Technology Corporation Limited
6*249ad85aSXiaojuan Yang  */
7*249ad85aSXiaojuan Yang 
8*249ad85aSXiaojuan Yang #define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
9*249ad85aSXiaojuan Yang OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
10*249ad85aSXiaojuan Yang 
11*249ad85aSXiaojuan Yang /* Msi irq start start from 64 to 255 */
12*249ad85aSXiaojuan Yang #define PCH_MSI_IRQ_START   64
13*249ad85aSXiaojuan Yang #define PCH_MSI_IRQ_END     255
14*249ad85aSXiaojuan Yang #define PCH_MSI_IRQ_NUM     192
15*249ad85aSXiaojuan Yang 
16*249ad85aSXiaojuan Yang struct LoongArchPCHMSI {
17*249ad85aSXiaojuan Yang     SysBusDevice parent_obj;
18*249ad85aSXiaojuan Yang     qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
19*249ad85aSXiaojuan Yang     MemoryRegion msi_mmio;
20*249ad85aSXiaojuan Yang };
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