1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch ipi interrupt header files 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #ifndef HW_LOONGARCH_IPI_H 9 #define HW_LOONGARCH_IPI_H 10 11 #include "hw/sysbus.h" 12 13 /* Mainy used by iocsr read and write */ 14 #define SMP_IPI_MAILBOX 0x1000ULL 15 #define CORE_STATUS_OFF 0x0 16 #define CORE_EN_OFF 0x4 17 #define CORE_SET_OFF 0x8 18 #define CORE_CLEAR_OFF 0xc 19 #define CORE_BUF_20 0x20 20 #define CORE_BUF_28 0x28 21 #define CORE_BUF_30 0x30 22 #define CORE_BUF_38 0x38 23 #define IOCSR_IPI_SEND 0x40 24 #define IOCSR_MAIL_SEND 0x48 25 #define IOCSR_ANY_SEND 0x158 26 27 #define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) 28 #define MAIL_SEND_OFFSET 0 29 #define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) 30 31 #define MAX_IPI_CORE_NUM 4 32 #define MAX_IPI_MBX_NUM 4 33 34 #define TYPE_LOONGARCH_IPI "loongarch_ipi" 35 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI) 36 37 typedef struct IPICore { 38 uint32_t status; 39 uint32_t en; 40 uint32_t set; 41 uint32_t clear; 42 /* 64bit buf divide into 2 32bit buf */ 43 uint32_t buf[MAX_IPI_MBX_NUM * 2]; 44 qemu_irq irq; 45 } IPICore; 46 47 struct LoongArchIPI { 48 SysBusDevice parent_obj; 49 MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM]; 50 MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM]; 51 }; 52 53 #endif 54