1 /* 2 * i.MX31 Vectored Interrupt Controller 3 * 4 * Note this is NOT the PL192 provided by ARM, but 5 * a custom implementation by Freescale. 6 * 7 * Copyright (c) 2008 OKL 8 * Copyright (c) 2011 NICTA Pty Ltd 9 * Originally written by Hans Jiang 10 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 11 * 12 * This code is licensed under the GPL version 2 or later. See 13 * the COPYING file in the top-level directory. 14 * 15 * TODO: implement vectors. 16 */ 17 #ifndef IMX_AVIC_H 18 #define IMX_AVIC_H 19 20 #include "hw/sysbus.h" 21 #include "qom/object.h" 22 23 #define TYPE_IMX_AVIC "imx.avic" 24 typedef struct IMXAVICState IMXAVICState; 25 DECLARE_INSTANCE_CHECKER(IMXAVICState, IMX_AVIC, 26 TYPE_IMX_AVIC) 27 28 #define IMX_AVIC_NUM_IRQS 64 29 30 /* Interrupt Control Bits */ 31 #define ABFLAG (1<<25) 32 #define ABFEN (1<<24) 33 #define NIDIS (1<<22) /* Normal Interrupt disable */ 34 #define FIDIS (1<<21) /* Fast interrupt disable */ 35 #define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */ 36 #define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */ 37 #define NM (1<<18) /* Normal interrupt mode */ 38 39 #define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4) 40 #define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD) 41 42 struct IMXAVICState { 43 /*< private >*/ 44 SysBusDevice parent_obj; 45 46 /*< public >*/ 47 MemoryRegion iomem; 48 uint64_t pending; 49 uint64_t enabled; 50 uint64_t is_fiq; 51 uint32_t intcntl; 52 uint32_t intmask; 53 qemu_irq irq; 54 qemu_irq fiq; 55 uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */ 56 }; 57 58 #endif /* IMX_AVIC_H */ 59