1 /* 2 * ARMv7M NVIC object 3 * 4 * Copyright (c) 2017 Linaro Ltd 5 * Written by Peter Maydell <peter.maydell@linaro.org> 6 * 7 * This code is licensed under the GPL version 2 or later. 8 */ 9 10 #ifndef HW_ARM_ARMV7M_NVIC_H 11 #define HW_ARM_ARMV7M_NVIC_H 12 13 #include "target/arm/cpu.h" 14 #include "hw/sysbus.h" 15 #include "hw/timer/armv7m_systick.h" 16 17 #define TYPE_NVIC "armv7m_nvic" 18 19 #define NVIC(obj) \ 20 OBJECT_CHECK(NVICState, (obj), TYPE_NVIC) 21 22 /* Highest permitted number of exceptions (architectural limit) */ 23 #define NVIC_MAX_VECTORS 512 24 /* Number of internal exceptions */ 25 #define NVIC_INTERNAL_VECTORS 16 26 27 typedef struct VecInfo { 28 /* Exception priorities can range from -3 to 255; only the unmodifiable 29 * priority values for RESET, NMI and HardFault can be negative. 30 */ 31 int16_t prio; 32 uint8_t enabled; 33 uint8_t pending; 34 uint8_t active; 35 uint8_t level; /* exceptions <=15 never set level */ 36 } VecInfo; 37 38 typedef struct NVICState { 39 /*< private >*/ 40 SysBusDevice parent_obj; 41 /*< public >*/ 42 43 ARMCPU *cpu; 44 45 VecInfo vectors[NVIC_MAX_VECTORS]; 46 /* If the v8M security extension is implemented, some of the internal 47 * exceptions are banked between security states (ie there exists both 48 * a Secure and a NonSecure version of the exception and its state): 49 * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV) 50 * The rest (including all the external exceptions) are not banked, though 51 * they may be configurable to target either Secure or NonSecure state. 52 * We store the secure exception state in sec_vectors[] for the banked 53 * exceptions, and otherwise use only vectors[] (including for exceptions 54 * like SecureFault that unconditionally target Secure state). 55 * Entries in sec_vectors[] for non-banked exception numbers are unused. 56 */ 57 VecInfo sec_vectors[NVIC_INTERNAL_VECTORS]; 58 /* The PRIGROUP field in AIRCR is banked */ 59 uint32_t prigroup[M_REG_NUM_BANKS]; 60 61 /* v8M NVIC_ITNS state (stored as a bool per bit) */ 62 bool itns[NVIC_MAX_VECTORS]; 63 64 /* The following fields are all cached state that can be recalculated 65 * from the vectors[] and sec_vectors[] arrays and the prigroup field: 66 * - vectpending 67 * - vectpending_is_secure 68 * - exception_prio 69 * - vectpending_prio 70 */ 71 unsigned int vectpending; /* highest prio pending enabled exception */ 72 /* true if vectpending is a banked secure exception, ie it is in 73 * sec_vectors[] rather than vectors[] 74 */ 75 bool vectpending_is_s_banked; 76 int exception_prio; /* group prio of the highest prio active exception */ 77 int vectpending_prio; /* group prio of the exeception in vectpending */ 78 79 MemoryRegion sysregmem; 80 MemoryRegion sysreg_ns_mem; 81 MemoryRegion systickmem; 82 MemoryRegion systick_ns_mem; 83 MemoryRegion container; 84 85 uint32_t num_irq; 86 qemu_irq excpout; 87 qemu_irq sysresetreq; 88 89 SysTickState systick[M_REG_NUM_BANKS]; 90 } NVICState; 91 92 #endif 93