1 /* 2 * ARMv7M NVIC object 3 * 4 * Copyright (c) 2017 Linaro Ltd 5 * Written by Peter Maydell <peter.maydell@linaro.org> 6 * 7 * This code is licensed under the GPL version 2 or later. 8 */ 9 10 #ifndef HW_ARM_ARMV7M_NVIC_H 11 #define HW_ARM_ARMV7M_NVIC_H 12 13 #include "target/arm/cpu.h" 14 #include "hw/sysbus.h" 15 #include "hw/timer/armv7m_systick.h" 16 #include "qom/object.h" 17 18 #define TYPE_NVIC "armv7m_nvic" 19 OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) 20 21 /* Highest permitted number of exceptions (architectural limit) */ 22 #define NVIC_MAX_VECTORS 512 23 /* Number of internal exceptions */ 24 #define NVIC_INTERNAL_VECTORS 16 25 26 typedef struct VecInfo { 27 /* Exception priorities can range from -3 to 255; only the unmodifiable 28 * priority values for RESET, NMI and HardFault can be negative. 29 */ 30 int16_t prio; 31 uint8_t enabled; 32 uint8_t pending; 33 uint8_t active; 34 uint8_t level; /* exceptions <=15 never set level */ 35 } VecInfo; 36 37 struct NVICState { 38 /*< private >*/ 39 SysBusDevice parent_obj; 40 /*< public >*/ 41 42 ARMCPU *cpu; 43 44 VecInfo vectors[NVIC_MAX_VECTORS]; 45 /* If the v8M security extension is implemented, some of the internal 46 * exceptions are banked between security states (ie there exists both 47 * a Secure and a NonSecure version of the exception and its state): 48 * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV) 49 * The rest (including all the external exceptions) are not banked, though 50 * they may be configurable to target either Secure or NonSecure state. 51 * We store the secure exception state in sec_vectors[] for the banked 52 * exceptions, and otherwise use only vectors[] (including for exceptions 53 * like SecureFault that unconditionally target Secure state). 54 * Entries in sec_vectors[] for non-banked exception numbers are unused. 55 */ 56 VecInfo sec_vectors[NVIC_INTERNAL_VECTORS]; 57 /* The PRIGROUP field in AIRCR is banked */ 58 uint32_t prigroup[M_REG_NUM_BANKS]; 59 uint8_t num_prio_bits; 60 61 /* v8M NVIC_ITNS state (stored as a bool per bit) */ 62 bool itns[NVIC_MAX_VECTORS]; 63 64 /* The following fields are all cached state that can be recalculated 65 * from the vectors[] and sec_vectors[] arrays and the prigroup field: 66 * - vectpending 67 * - vectpending_is_secure 68 * - exception_prio 69 * - vectpending_prio 70 */ 71 unsigned int vectpending; /* highest prio pending enabled exception */ 72 /* true if vectpending is a banked secure exception, ie it is in 73 * sec_vectors[] rather than vectors[] 74 */ 75 bool vectpending_is_s_banked; 76 int exception_prio; /* group prio of the highest prio active exception */ 77 int vectpending_prio; /* group prio of the exeception in vectpending */ 78 79 MemoryRegion sysregmem; 80 81 uint32_t num_irq; 82 qemu_irq excpout; 83 qemu_irq sysresetreq; 84 }; 85 86 #endif 87