1 /*
2  * ARM GIC support
3  *
4  * Copyright (c) 2012 Linaro Limited
5  * Copyright (c) 2015 Huawei.
6  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
7  * Written by Peter Maydell
8  * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation, either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License along
21  * with this program; if not, see <http://www.gnu.org/licenses/>.
22  */
23 
24 #ifndef HW_ARM_GICV3_COMMON_H
25 #define HW_ARM_GICV3_COMMON_H
26 
27 #include "hw/sysbus.h"
28 #include "hw/intc/arm_gic_common.h"
29 #include "qom/object.h"
30 
31 /*
32  * Maximum number of possible interrupts, determined by the GIC architecture.
33  * Note that this does not include LPIs. When implemented, these should be
34  * dealt with separately.
35  */
36 #define GICV3_MAXIRQ 1020
37 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
38 
39 #define GICV3_LPI_INTID_START 8192
40 
41 #define GICV3_REDIST_SIZE 0x20000
42 
43 /* Number of SGI target-list bits */
44 #define GICV3_TARGETLIST_BITS 16
45 
46 /* Maximum number of list registers (architectural limit) */
47 #define GICV3_LR_MAX 16
48 
49 /* Minimum BPR for Secure, or when security not enabled */
50 #define GIC_MIN_BPR 0
51 /* Minimum BPR for Nonsecure when security is enabled */
52 #define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1)
53 
54 /* For some distributor fields we want to model the array of 32-bit
55  * register values which hold various bitmaps corresponding to enabled,
56  * pending, etc bits. These macros and functions facilitate that; the
57  * APIs are generally modelled on the generic bitmap.h functions
58  * (which are unsuitable here because they use 'unsigned long' as the
59  * underlying storage type, which is very awkward when you need to
60  * access the data as 32-bit values.)
61  * Each bitmap contains a bit for each interrupt. Although there is
62  * space for the PPIs and SGIs, those bits (the first 32) are never
63  * used as that state lives in the redistributor. The unused bits are
64  * provided purely so that interrupt X's state is always in bit X; this
65  * avoids bugs where we forget to subtract GIC_INTERNAL from an
66  * interrupt number.
67  */
68 #define GICV3_BMP_SIZE DIV_ROUND_UP(GICV3_MAXIRQ, 32)
69 
70 #define GIC_DECLARE_BITMAP(name) \
71     uint32_t name[GICV3_BMP_SIZE]
72 
73 #define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
74 #define GIC_BIT_WORD(nr) ((nr) / 32)
75 
76 static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
77 {
78     uint32_t mask = GIC_BIT_MASK(nr);
79     uint32_t *p = addr + GIC_BIT_WORD(nr);
80 
81     *p |= mask;
82 }
83 
84 static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
85 {
86     uint32_t mask = GIC_BIT_MASK(nr);
87     uint32_t *p = addr + GIC_BIT_WORD(nr);
88 
89     *p &= ~mask;
90 }
91 
92 static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
93 {
94     return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
95 }
96 
97 static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
98 {
99     uint32_t mask = GIC_BIT_MASK(nr);
100     uint32_t *p = addr + GIC_BIT_WORD(nr);
101 
102     *p &= ~mask;
103     *p |= (val & 1U) << (nr % 32);
104 }
105 
106 /* Return a pointer to the 32-bit word containing the specified bit. */
107 static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
108 {
109     return addr + GIC_BIT_WORD(nr);
110 }
111 
112 typedef struct GICv3State GICv3State;
113 typedef struct GICv3CPUState GICv3CPUState;
114 
115 /* Some CPU interface registers come in three flavours:
116  * Group0, Group1 (Secure) and Group1 (NonSecure)
117  * (where the latter two are exposed as a single banked system register).
118  * In the state struct they are implemented as a 3-element array which
119  * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
120  * If the CPU doesn't support EL3 then the G1 element is unused.
121  *
122  * These constants are also used to communicate the group to use for
123  * an interrupt or SGI when it is passed between the cpu interface and
124  * the redistributor or distributor. For those purposes the receiving end
125  * must be prepared to cope with a Group 1 Secure interrupt even if it does
126  * not have security support enabled, because security can be disabled
127  * independently in the CPU and in the GIC. In that case the receiver should
128  * treat an incoming Group 1 Secure interrupt as if it were Group 0.
129  * (This architectural requirement is why the _G1 element is the unused one
130  * in a no-EL3 CPU:  we would otherwise have to translate back and forth
131  * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.)
132  */
133 #define GICV3_G0 0
134 #define GICV3_G1 1
135 #define GICV3_G1NS 2
136 
137 /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not
138  * group-related, so those indices are just 0 for S and 1 for NS.
139  * (If the CPU or the GIC, respectively, don't support the Security
140  * extensions then the S element is unused.)
141  */
142 #define GICV3_S 0
143 #define GICV3_NS 1
144 
145 typedef struct {
146     int irq;
147     uint8_t prio;
148     int grp;
149 } PendingIrq;
150 
151 struct GICv3CPUState {
152     GICv3State *gic;
153     CPUState *cpu;
154     qemu_irq parent_irq;
155     qemu_irq parent_fiq;
156     qemu_irq parent_virq;
157     qemu_irq parent_vfiq;
158 
159     /* Redistributor */
160     uint32_t level;                  /* Current IRQ level */
161     /* RD_base page registers */
162     uint32_t gicr_ctlr;
163     uint64_t gicr_typer;
164     uint32_t gicr_statusr[2];
165     uint32_t gicr_waker;
166     uint64_t gicr_propbaser;
167     uint64_t gicr_pendbaser;
168     /* SGI_base page registers */
169     uint32_t gicr_igroupr0;
170     uint32_t gicr_ienabler0;
171     uint32_t gicr_ipendr0;
172     uint32_t gicr_iactiver0;
173     uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
174     uint32_t gicr_igrpmodr0;
175     uint32_t gicr_nsacr;
176     uint8_t gicr_ipriorityr[GIC_INTERNAL];
177 
178     /* CPU interface */
179     uint64_t icc_sre_el1;
180     uint64_t icc_ctlr_el1[2];
181     uint64_t icc_pmr_el1;
182     uint64_t icc_bpr[3];
183     uint64_t icc_apr[3][4];
184     uint64_t icc_igrpen[3];
185     uint64_t icc_ctlr_el3;
186 
187     /* Virtualization control interface */
188     uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */
189     uint64_t ich_hcr_el2;
190     uint64_t ich_lr_el2[GICV3_LR_MAX];
191     uint64_t ich_vmcr_el2;
192 
193     /* Properties of the CPU interface. These are initialized from
194      * the settings in the CPU proper.
195      * If the number of implemented list registers is 0 then the
196      * virtualization support is not implemented.
197      */
198     int num_list_regs;
199     int vpribits; /* number of virtual priority bits */
200     int vprebits; /* number of virtual preemption bits */
201 
202     /* Current highest priority pending interrupt for this CPU.
203      * This is cached information that can be recalculated from the
204      * real state above; it doesn't need to be migrated.
205      */
206     PendingIrq hppi;
207 
208     /*
209      * Cached information recalculated from LPI tables
210      * in guest memory
211      */
212     PendingIrq hpplpi;
213 
214     /* This is temporary working state, to avoid a malloc in gicv3_update() */
215     bool seenbetter;
216 };
217 
218 struct GICv3State {
219     /*< private >*/
220     SysBusDevice parent_obj;
221     /*< public >*/
222 
223     MemoryRegion iomem_dist; /* Distributor */
224     MemoryRegion *iomem_redist; /* Redistributor Regions */
225     uint32_t *redist_region_count; /* redistributor count within each region */
226     uint32_t nb_redist_regions; /* number of redist regions */
227 
228     uint32_t num_cpu;
229     uint32_t num_irq;
230     uint32_t revision;
231     bool lpi_enable;
232     bool security_extn;
233     bool irq_reset_nonsecure;
234     bool gicd_no_migration_shift_bug;
235 
236     int dev_fd; /* kvm device fd if backed by kvm vgic support */
237     Error *migration_blocker;
238 
239     MemoryRegion *dma;
240     AddressSpace dma_as;
241 
242     /* Distributor */
243 
244     /* for a GIC with the security extensions the NS banked version of this
245      * register is just an alias of bit 1 of the S banked version.
246      */
247     uint32_t gicd_ctlr;
248     uint32_t gicd_statusr[2];
249     GIC_DECLARE_BITMAP(group);        /* GICD_IGROUPR */
250     GIC_DECLARE_BITMAP(grpmod);       /* GICD_IGRPMODR */
251     GIC_DECLARE_BITMAP(enabled);      /* GICD_ISENABLER */
252     GIC_DECLARE_BITMAP(pending);      /* GICD_ISPENDR */
253     GIC_DECLARE_BITMAP(active);       /* GICD_ISACTIVER */
254     GIC_DECLARE_BITMAP(level);        /* Current level */
255     GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */
256     uint8_t gicd_ipriority[GICV3_MAXIRQ];
257     uint64_t gicd_irouter[GICV3_MAXIRQ];
258     /* Cached information: pointer to the cpu i/f for the CPUs specified
259      * in the IROUTER registers
260      */
261     GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
262     uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
263 
264     GICv3CPUState *cpu;
265 };
266 
267 #define GICV3_BITMAP_ACCESSORS(BMP)                                     \
268     static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq)   \
269     {                                                                   \
270         gic_bmp_set_bit(irq, s->BMP);                                   \
271     }                                                                   \
272     static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq)   \
273     {                                                                   \
274         return gic_bmp_test_bit(irq, s->BMP);                           \
275     }                                                                   \
276     static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
277     {                                                                   \
278         gic_bmp_clear_bit(irq, s->BMP);                                 \
279     }                                                                   \
280     static inline void gicv3_gicd_##BMP##_replace(GICv3State *s,        \
281                                                   int irq, int value)   \
282     {                                                                   \
283         gic_bmp_replace_bit(irq, s->BMP, value);                        \
284     }
285 
286 GICV3_BITMAP_ACCESSORS(group)
287 GICV3_BITMAP_ACCESSORS(grpmod)
288 GICV3_BITMAP_ACCESSORS(enabled)
289 GICV3_BITMAP_ACCESSORS(pending)
290 GICV3_BITMAP_ACCESSORS(active)
291 GICV3_BITMAP_ACCESSORS(level)
292 GICV3_BITMAP_ACCESSORS(edge_trigger)
293 
294 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
295 typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
296 DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,
297                      ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON)
298 
299 struct ARMGICv3CommonClass {
300     /*< private >*/
301     SysBusDeviceClass parent_class;
302     /*< public >*/
303 
304     void (*pre_save)(GICv3State *s);
305     void (*post_load)(GICv3State *s);
306 };
307 
308 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
309                               const MemoryRegionOps *ops, Error **errp);
310 
311 #endif
312