1 /* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef HW_ARM_GICV3_COMMON_H 25 #define HW_ARM_GICV3_COMMON_H 26 27 #include "hw/sysbus.h" 28 #include "hw/intc/arm_gic_common.h" 29 30 /* 31 * Maximum number of possible interrupts, determined by the GIC architecture. 32 * Note that this does not include LPIs. When implemented, these should be 33 * dealt with separately. 34 */ 35 #define GICV3_MAXIRQ 1020 36 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) 37 38 /* Number of SGI target-list bits */ 39 #define GICV3_TARGETLIST_BITS 16 40 41 /* Maximum number of list registers (architectural limit) */ 42 #define GICV3_LR_MAX 16 43 44 /* Minimum BPR for Secure, or when security not enabled */ 45 #define GIC_MIN_BPR 0 46 /* Minimum BPR for Nonsecure when security is enabled */ 47 #define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1) 48 49 /* For some distributor fields we want to model the array of 32-bit 50 * register values which hold various bitmaps corresponding to enabled, 51 * pending, etc bits. These macros and functions facilitate that; the 52 * APIs are generally modelled on the generic bitmap.h functions 53 * (which are unsuitable here because they use 'unsigned long' as the 54 * underlying storage type, which is very awkward when you need to 55 * access the data as 32-bit values.) 56 * Each bitmap contains a bit for each interrupt. Although there is 57 * space for the PPIs and SGIs, those bits (the first 32) are never 58 * used as that state lives in the redistributor. The unused bits are 59 * provided purely so that interrupt X's state is always in bit X; this 60 * avoids bugs where we forget to subtract GIC_INTERNAL from an 61 * interrupt number. 62 */ 63 #define GICV3_BMP_SIZE (DIV_ROUND_UP(GICV3_MAXIRQ, 32)) 64 65 #define GIC_DECLARE_BITMAP(name) \ 66 uint32_t name[GICV3_BMP_SIZE] 67 68 #define GIC_BIT_MASK(nr) (1U << ((nr) % 32)) 69 #define GIC_BIT_WORD(nr) ((nr) / 32) 70 71 static inline void gic_bmp_set_bit(int nr, uint32_t *addr) 72 { 73 uint32_t mask = GIC_BIT_MASK(nr); 74 uint32_t *p = addr + GIC_BIT_WORD(nr); 75 76 *p |= mask; 77 } 78 79 static inline void gic_bmp_clear_bit(int nr, uint32_t *addr) 80 { 81 uint32_t mask = GIC_BIT_MASK(nr); 82 uint32_t *p = addr + GIC_BIT_WORD(nr); 83 84 *p &= ~mask; 85 } 86 87 static inline int gic_bmp_test_bit(int nr, const uint32_t *addr) 88 { 89 return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31)); 90 } 91 92 static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val) 93 { 94 uint32_t mask = GIC_BIT_MASK(nr); 95 uint32_t *p = addr + GIC_BIT_WORD(nr); 96 97 *p &= ~mask; 98 *p |= (val & 1U) << (nr % 32); 99 } 100 101 /* Return a pointer to the 32-bit word containing the specified bit. */ 102 static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr) 103 { 104 return addr + GIC_BIT_WORD(nr); 105 } 106 107 typedef struct GICv3State GICv3State; 108 typedef struct GICv3CPUState GICv3CPUState; 109 110 /* Some CPU interface registers come in three flavours: 111 * Group0, Group1 (Secure) and Group1 (NonSecure) 112 * (where the latter two are exposed as a single banked system register). 113 * In the state struct they are implemented as a 3-element array which 114 * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants. 115 * If the CPU doesn't support EL3 then the G1 element is unused. 116 * 117 * These constants are also used to communicate the group to use for 118 * an interrupt or SGI when it is passed between the cpu interface and 119 * the redistributor or distributor. For those purposes the receiving end 120 * must be prepared to cope with a Group 1 Secure interrupt even if it does 121 * not have security support enabled, because security can be disabled 122 * independently in the CPU and in the GIC. In that case the receiver should 123 * treat an incoming Group 1 Secure interrupt as if it were Group 0. 124 * (This architectural requirement is why the _G1 element is the unused one 125 * in a no-EL3 CPU: we would otherwise have to translate back and forth 126 * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.) 127 */ 128 #define GICV3_G0 0 129 #define GICV3_G1 1 130 #define GICV3_G1NS 2 131 132 /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not 133 * group-related, so those indices are just 0 for S and 1 for NS. 134 * (If the CPU or the GIC, respectively, don't support the Security 135 * extensions then the S element is unused.) 136 */ 137 #define GICV3_S 0 138 #define GICV3_NS 1 139 140 typedef struct { 141 int irq; 142 uint8_t prio; 143 int grp; 144 } PendingIrq; 145 146 struct GICv3CPUState { 147 GICv3State *gic; 148 CPUState *cpu; 149 qemu_irq parent_irq; 150 qemu_irq parent_fiq; 151 qemu_irq parent_virq; 152 qemu_irq parent_vfiq; 153 qemu_irq maintenance_irq; 154 155 /* Redistributor */ 156 uint32_t level; /* Current IRQ level */ 157 /* RD_base page registers */ 158 uint32_t gicr_ctlr; 159 uint64_t gicr_typer; 160 uint32_t gicr_statusr[2]; 161 uint32_t gicr_waker; 162 uint64_t gicr_propbaser; 163 uint64_t gicr_pendbaser; 164 /* SGI_base page registers */ 165 uint32_t gicr_igroupr0; 166 uint32_t gicr_ienabler0; 167 uint32_t gicr_ipendr0; 168 uint32_t gicr_iactiver0; 169 uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ 170 uint32_t gicr_igrpmodr0; 171 uint32_t gicr_nsacr; 172 uint8_t gicr_ipriorityr[GIC_INTERNAL]; 173 174 /* CPU interface */ 175 uint64_t icc_sre_el1; 176 uint64_t icc_ctlr_el1[2]; 177 uint64_t icc_pmr_el1; 178 uint64_t icc_bpr[3]; 179 uint64_t icc_apr[3][4]; 180 uint64_t icc_igrpen[3]; 181 uint64_t icc_ctlr_el3; 182 183 /* Virtualization control interface */ 184 uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */ 185 uint64_t ich_hcr_el2; 186 uint64_t ich_lr_el2[GICV3_LR_MAX]; 187 uint64_t ich_vmcr_el2; 188 189 /* Properties of the CPU interface. These are initialized from 190 * the settings in the CPU proper. 191 * If the number of implemented list registers is 0 then the 192 * virtualization support is not implemented. 193 */ 194 int num_list_regs; 195 int vpribits; /* number of virtual priority bits */ 196 int vprebits; /* number of virtual preemption bits */ 197 198 /* Current highest priority pending interrupt for this CPU. 199 * This is cached information that can be recalculated from the 200 * real state above; it doesn't need to be migrated. 201 */ 202 PendingIrq hppi; 203 /* This is temporary working state, to avoid a malloc in gicv3_update() */ 204 bool seenbetter; 205 }; 206 207 struct GICv3State { 208 /*< private >*/ 209 SysBusDevice parent_obj; 210 /*< public >*/ 211 212 MemoryRegion iomem_dist; /* Distributor */ 213 MemoryRegion iomem_redist; /* Redistributors */ 214 215 uint32_t num_cpu; 216 uint32_t num_irq; 217 uint32_t revision; 218 bool security_extn; 219 bool irq_reset_nonsecure; 220 221 int dev_fd; /* kvm device fd if backed by kvm vgic support */ 222 Error *migration_blocker; 223 224 /* Distributor */ 225 226 /* for a GIC with the security extensions the NS banked version of this 227 * register is just an alias of bit 1 of the S banked version. 228 */ 229 uint32_t gicd_ctlr; 230 uint32_t gicd_statusr[2]; 231 GIC_DECLARE_BITMAP(group); /* GICD_IGROUPR */ 232 GIC_DECLARE_BITMAP(grpmod); /* GICD_IGRPMODR */ 233 GIC_DECLARE_BITMAP(enabled); /* GICD_ISENABLER */ 234 GIC_DECLARE_BITMAP(pending); /* GICD_ISPENDR */ 235 GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */ 236 GIC_DECLARE_BITMAP(level); /* Current level */ 237 GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */ 238 uint8_t gicd_ipriority[GICV3_MAXIRQ]; 239 uint64_t gicd_irouter[GICV3_MAXIRQ]; 240 /* Cached information: pointer to the cpu i/f for the CPUs specified 241 * in the IROUTER registers 242 */ 243 GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ]; 244 uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)]; 245 246 GICv3CPUState *cpu; 247 }; 248 249 #define GICV3_BITMAP_ACCESSORS(BMP) \ 250 static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \ 251 { \ 252 gic_bmp_set_bit(irq, s->BMP); \ 253 } \ 254 static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \ 255 { \ 256 return gic_bmp_test_bit(irq, s->BMP); \ 257 } \ 258 static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \ 259 { \ 260 gic_bmp_clear_bit(irq, s->BMP); \ 261 } \ 262 static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \ 263 int irq, int value) \ 264 { \ 265 gic_bmp_replace_bit(irq, s->BMP, value); \ 266 } 267 268 GICV3_BITMAP_ACCESSORS(group) 269 GICV3_BITMAP_ACCESSORS(grpmod) 270 GICV3_BITMAP_ACCESSORS(enabled) 271 GICV3_BITMAP_ACCESSORS(pending) 272 GICV3_BITMAP_ACCESSORS(active) 273 GICV3_BITMAP_ACCESSORS(level) 274 GICV3_BITMAP_ACCESSORS(edge_trigger) 275 276 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common" 277 #define ARM_GICV3_COMMON(obj) \ 278 OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON) 279 #define ARM_GICV3_COMMON_CLASS(klass) \ 280 OBJECT_CLASS_CHECK(ARMGICv3CommonClass, (klass), TYPE_ARM_GICV3_COMMON) 281 #define ARM_GICV3_COMMON_GET_CLASS(obj) \ 282 OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON) 283 284 typedef struct ARMGICv3CommonClass { 285 /*< private >*/ 286 SysBusDeviceClass parent_class; 287 /*< public >*/ 288 289 void (*pre_save)(GICv3State *s); 290 void (*post_load)(GICv3State *s); 291 } ARMGICv3CommonClass; 292 293 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, 294 const MemoryRegionOps *ops); 295 296 #endif 297