1 /* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Copyright (c) 2015 Huawei. 6 * Copyright (c) 2015 Samsung Electronics Co., Ltd. 7 * Written by Peter Maydell 8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation, either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef HW_ARM_GICV3_COMMON_H 25 #define HW_ARM_GICV3_COMMON_H 26 27 #include "hw/sysbus.h" 28 #include "hw/intc/arm_gic_common.h" 29 #include "qom/object.h" 30 31 /* 32 * Maximum number of possible interrupts, determined by the GIC architecture. 33 * Note that this does not include LPIs. When implemented, these should be 34 * dealt with separately. 35 */ 36 #define GICV3_MAXIRQ 1020 37 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) 38 39 #define GICV3_LPI_INTID_START 8192 40 41 /* 42 * The redistributor in GICv3 has two 64KB frames per CPU; in 43 * GICv4 it has four 64KB frames per CPU. 44 */ 45 #define GICV3_REDIST_SIZE 0x20000 46 #define GICV4_REDIST_SIZE 0x40000 47 48 /* Number of SGI target-list bits */ 49 #define GICV3_TARGETLIST_BITS 16 50 51 /* Maximum number of list registers (architectural limit) */ 52 #define GICV3_LR_MAX 16 53 54 /* 55 * For some distributor fields we want to model the array of 32-bit 56 * register values which hold various bitmaps corresponding to enabled, 57 * pending, etc bits. We use the set_bit32() etc family of functions 58 * from bitops.h for this. For a few cases we need to implement some 59 * extra operations. 60 * 61 * Each bitmap contains a bit for each interrupt. Although there is 62 * space for the PPIs and SGIs, those bits (the first 32) are never 63 * used as that state lives in the redistributor. The unused bits are 64 * provided purely so that interrupt X's state is always in bit X; this 65 * avoids bugs where we forget to subtract GIC_INTERNAL from an 66 * interrupt number. 67 */ 68 #define GIC_DECLARE_BITMAP(name) DECLARE_BITMAP32(name, GICV3_MAXIRQ) 69 #define GICV3_BMP_SIZE BITS_TO_U32S(GICV3_MAXIRQ) 70 71 static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val) 72 { 73 uint32_t mask = BIT32_MASK(nr); 74 uint32_t *p = addr + BIT32_WORD(nr); 75 76 *p &= ~mask; 77 *p |= (val & 1U) << (nr % 32); 78 } 79 80 /* Return a pointer to the 32-bit word containing the specified bit. */ 81 static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr) 82 { 83 return addr + BIT32_WORD(nr); 84 } 85 86 typedef struct GICv3State GICv3State; 87 typedef struct GICv3CPUState GICv3CPUState; 88 89 /* Some CPU interface registers come in three flavours: 90 * Group0, Group1 (Secure) and Group1 (NonSecure) 91 * (where the latter two are exposed as a single banked system register). 92 * In the state struct they are implemented as a 3-element array which 93 * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants. 94 * If the CPU doesn't support EL3 then the G1 element is unused. 95 * 96 * These constants are also used to communicate the group to use for 97 * an interrupt or SGI when it is passed between the cpu interface and 98 * the redistributor or distributor. For those purposes the receiving end 99 * must be prepared to cope with a Group 1 Secure interrupt even if it does 100 * not have security support enabled, because security can be disabled 101 * independently in the CPU and in the GIC. In that case the receiver should 102 * treat an incoming Group 1 Secure interrupt as if it were Group 0. 103 * (This architectural requirement is why the _G1 element is the unused one 104 * in a no-EL3 CPU: we would otherwise have to translate back and forth 105 * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.) 106 */ 107 #define GICV3_G0 0 108 #define GICV3_G1 1 109 #define GICV3_G1NS 2 110 111 /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not 112 * group-related, so those indices are just 0 for S and 1 for NS. 113 * (If the CPU or the GIC, respectively, don't support the Security 114 * extensions then the S element is unused.) 115 */ 116 #define GICV3_S 0 117 #define GICV3_NS 1 118 119 typedef struct { 120 int irq; 121 uint8_t prio; 122 int grp; 123 bool nmi; 124 } PendingIrq; 125 126 struct GICv3CPUState { 127 GICv3State *gic; 128 CPUState *cpu; 129 qemu_irq parent_irq; 130 qemu_irq parent_fiq; 131 qemu_irq parent_virq; 132 qemu_irq parent_vfiq; 133 qemu_irq parent_nmi; 134 qemu_irq parent_vnmi; 135 136 /* Redistributor */ 137 uint32_t level; /* Current IRQ level */ 138 /* RD_base page registers */ 139 uint32_t gicr_ctlr; 140 uint64_t gicr_typer; 141 uint32_t gicr_statusr[2]; 142 uint32_t gicr_waker; 143 uint64_t gicr_propbaser; 144 uint64_t gicr_pendbaser; 145 /* SGI_base page registers */ 146 uint32_t gicr_igroupr0; 147 uint32_t gicr_ienabler0; 148 uint32_t gicr_ipendr0; 149 uint32_t gicr_iactiver0; 150 uint32_t gicr_inmir0; 151 uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ 152 uint32_t gicr_igrpmodr0; 153 uint32_t gicr_nsacr; 154 uint8_t gicr_ipriorityr[GIC_INTERNAL]; 155 /* VLPI_base page registers */ 156 uint64_t gicr_vpropbaser; 157 uint64_t gicr_vpendbaser; 158 159 /* CPU interface */ 160 uint64_t icc_sre_el1; 161 uint64_t icc_ctlr_el1[2]; 162 uint64_t icc_pmr_el1; 163 uint64_t icc_bpr[3]; 164 uint64_t icc_apr[3][4]; 165 uint64_t icc_igrpen[3]; 166 uint64_t icc_ctlr_el3; 167 168 /* Virtualization control interface */ 169 uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */ 170 uint64_t ich_hcr_el2; 171 uint64_t ich_lr_el2[GICV3_LR_MAX]; 172 uint64_t ich_vmcr_el2; 173 174 /* Properties of the CPU interface. These are initialized from 175 * the settings in the CPU proper. 176 * If the number of implemented list registers is 0 then the 177 * virtualization support is not implemented. 178 */ 179 int num_list_regs; 180 int vpribits; /* number of virtual priority bits */ 181 int vprebits; /* number of virtual preemption bits */ 182 int pribits; /* number of physical priority bits */ 183 int prebits; /* number of physical preemption bits */ 184 185 /* Current highest priority pending interrupt for this CPU. 186 * This is cached information that can be recalculated from the 187 * real state above; it doesn't need to be migrated. 188 */ 189 PendingIrq hppi; 190 191 /* 192 * Cached information recalculated from LPI tables 193 * in guest memory 194 */ 195 PendingIrq hpplpi; 196 197 /* Cached information recalculated from vLPI tables in guest memory */ 198 PendingIrq hppvlpi; 199 200 /* This is temporary working state, to avoid a malloc in gicv3_update() */ 201 bool seenbetter; 202 203 /* 204 * Whether the CPU interface has NMI support (FEAT_GICv3_NMI). The 205 * CPU interface may support NMIs even when the GIC proper (what the 206 * spec calls the IRI; the redistributors and distributor) does not. 207 */ 208 bool nmi_support; 209 }; 210 211 /* 212 * The redistributor pages might be split into more than one region 213 * on some machine types if there are many CPUs. 214 */ 215 typedef struct GICv3RedistRegion { 216 GICv3State *gic; 217 MemoryRegion iomem; 218 uint32_t cpuidx; /* index of first CPU this region covers */ 219 } GICv3RedistRegion; 220 221 struct GICv3State { 222 /*< private >*/ 223 SysBusDevice parent_obj; 224 /*< public >*/ 225 226 MemoryRegion iomem_dist; /* Distributor */ 227 GICv3RedistRegion *redist_regions; /* Redistributor Regions */ 228 uint32_t *redist_region_count; /* redistributor count within each region */ 229 uint32_t nb_redist_regions; /* number of redist regions */ 230 231 uint32_t num_cpu; 232 uint32_t num_irq; 233 uint32_t revision; 234 bool lpi_enable; 235 bool nmi_support; 236 bool security_extn; 237 bool force_8bit_prio; 238 bool irq_reset_nonsecure; 239 bool gicd_no_migration_shift_bug; 240 241 int dev_fd; /* kvm device fd if backed by kvm vgic support */ 242 Error *migration_blocker; 243 244 MemoryRegion *dma; 245 AddressSpace dma_as; 246 247 /* Distributor */ 248 249 /* for a GIC with the security extensions the NS banked version of this 250 * register is just an alias of bit 1 of the S banked version. 251 */ 252 uint32_t gicd_ctlr; 253 uint32_t gicd_statusr[2]; 254 GIC_DECLARE_BITMAP(group); /* GICD_IGROUPR */ 255 GIC_DECLARE_BITMAP(grpmod); /* GICD_IGRPMODR */ 256 GIC_DECLARE_BITMAP(enabled); /* GICD_ISENABLER */ 257 GIC_DECLARE_BITMAP(pending); /* GICD_ISPENDR */ 258 GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */ 259 GIC_DECLARE_BITMAP(level); /* Current level */ 260 GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */ 261 GIC_DECLARE_BITMAP(nmi); /* GICD_INMIR */ 262 uint8_t gicd_ipriority[GICV3_MAXIRQ]; 263 uint64_t gicd_irouter[GICV3_MAXIRQ]; 264 /* Cached information: pointer to the cpu i/f for the CPUs specified 265 * in the IROUTER registers 266 */ 267 GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ]; 268 uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)]; 269 270 GICv3CPUState *cpu; 271 /* List of all ITSes connected to this GIC */ 272 GPtrArray *itslist; 273 }; 274 275 #define GICV3_BITMAP_ACCESSORS(BMP) \ 276 static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \ 277 { \ 278 set_bit32(irq, s->BMP); \ 279 } \ 280 static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \ 281 { \ 282 return test_bit32(irq, s->BMP); \ 283 } \ 284 static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \ 285 { \ 286 clear_bit32(irq, s->BMP); \ 287 } \ 288 static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \ 289 int irq, int value) \ 290 { \ 291 gic_bmp_replace_bit(irq, s->BMP, value); \ 292 } 293 294 GICV3_BITMAP_ACCESSORS(group) 295 GICV3_BITMAP_ACCESSORS(grpmod) 296 GICV3_BITMAP_ACCESSORS(enabled) 297 GICV3_BITMAP_ACCESSORS(pending) 298 GICV3_BITMAP_ACCESSORS(active) 299 GICV3_BITMAP_ACCESSORS(level) 300 GICV3_BITMAP_ACCESSORS(edge_trigger) 301 GICV3_BITMAP_ACCESSORS(nmi) 302 303 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common" 304 typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; 305 DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass, 306 ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON) 307 308 struct ARMGICv3CommonClass { 309 /*< private >*/ 310 SysBusDeviceClass parent_class; 311 /*< public >*/ 312 313 void (*pre_save)(GICv3State *s); 314 void (*post_load)(GICv3State *s); 315 }; 316 317 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, 318 const MemoryRegionOps *ops); 319 320 /** 321 * gicv3_class_name 322 * 323 * Return name of GICv3 class to use depending on whether KVM acceleration is 324 * in use. May throw an error if the chosen implementation is not available. 325 * 326 * Returns: class name to use 327 */ 328 const char *gicv3_class_name(void); 329 330 #endif 331