1 /*
2  * ARM GIC support
3  *
4  * Copyright (c) 2012 Linaro Limited
5  * Copyright (c) 2015 Huawei.
6  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
7  * Written by Peter Maydell
8  * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation, either version 2 of the License, or
13  * (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License along
21  * with this program; if not, see <http://www.gnu.org/licenses/>.
22  */
23 
24 #ifndef HW_ARM_GICV3_COMMON_H
25 #define HW_ARM_GICV3_COMMON_H
26 
27 #include "hw/sysbus.h"
28 #include "hw/intc/arm_gic_common.h"
29 #include "qom/object.h"
30 
31 /*
32  * Maximum number of possible interrupts, determined by the GIC architecture.
33  * Note that this does not include LPIs. When implemented, these should be
34  * dealt with separately.
35  */
36 #define GICV3_MAXIRQ 1020
37 #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
38 
39 #define GICV3_REDIST_SIZE 0x20000
40 
41 /* Number of SGI target-list bits */
42 #define GICV3_TARGETLIST_BITS 16
43 
44 /* Maximum number of list registers (architectural limit) */
45 #define GICV3_LR_MAX 16
46 
47 /* Minimum BPR for Secure, or when security not enabled */
48 #define GIC_MIN_BPR 0
49 /* Minimum BPR for Nonsecure when security is enabled */
50 #define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1)
51 
52 /* For some distributor fields we want to model the array of 32-bit
53  * register values which hold various bitmaps corresponding to enabled,
54  * pending, etc bits. These macros and functions facilitate that; the
55  * APIs are generally modelled on the generic bitmap.h functions
56  * (which are unsuitable here because they use 'unsigned long' as the
57  * underlying storage type, which is very awkward when you need to
58  * access the data as 32-bit values.)
59  * Each bitmap contains a bit for each interrupt. Although there is
60  * space for the PPIs and SGIs, those bits (the first 32) are never
61  * used as that state lives in the redistributor. The unused bits are
62  * provided purely so that interrupt X's state is always in bit X; this
63  * avoids bugs where we forget to subtract GIC_INTERNAL from an
64  * interrupt number.
65  */
66 #define GICV3_BMP_SIZE DIV_ROUND_UP(GICV3_MAXIRQ, 32)
67 
68 #define GIC_DECLARE_BITMAP(name) \
69     uint32_t name[GICV3_BMP_SIZE]
70 
71 #define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
72 #define GIC_BIT_WORD(nr) ((nr) / 32)
73 
74 static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
75 {
76     uint32_t mask = GIC_BIT_MASK(nr);
77     uint32_t *p = addr + GIC_BIT_WORD(nr);
78 
79     *p |= mask;
80 }
81 
82 static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
83 {
84     uint32_t mask = GIC_BIT_MASK(nr);
85     uint32_t *p = addr + GIC_BIT_WORD(nr);
86 
87     *p &= ~mask;
88 }
89 
90 static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
91 {
92     return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
93 }
94 
95 static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
96 {
97     uint32_t mask = GIC_BIT_MASK(nr);
98     uint32_t *p = addr + GIC_BIT_WORD(nr);
99 
100     *p &= ~mask;
101     *p |= (val & 1U) << (nr % 32);
102 }
103 
104 /* Return a pointer to the 32-bit word containing the specified bit. */
105 static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
106 {
107     return addr + GIC_BIT_WORD(nr);
108 }
109 
110 typedef struct GICv3State GICv3State;
111 typedef struct GICv3CPUState GICv3CPUState;
112 
113 /* Some CPU interface registers come in three flavours:
114  * Group0, Group1 (Secure) and Group1 (NonSecure)
115  * (where the latter two are exposed as a single banked system register).
116  * In the state struct they are implemented as a 3-element array which
117  * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
118  * If the CPU doesn't support EL3 then the G1 element is unused.
119  *
120  * These constants are also used to communicate the group to use for
121  * an interrupt or SGI when it is passed between the cpu interface and
122  * the redistributor or distributor. For those purposes the receiving end
123  * must be prepared to cope with a Group 1 Secure interrupt even if it does
124  * not have security support enabled, because security can be disabled
125  * independently in the CPU and in the GIC. In that case the receiver should
126  * treat an incoming Group 1 Secure interrupt as if it were Group 0.
127  * (This architectural requirement is why the _G1 element is the unused one
128  * in a no-EL3 CPU:  we would otherwise have to translate back and forth
129  * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.)
130  */
131 #define GICV3_G0 0
132 #define GICV3_G1 1
133 #define GICV3_G1NS 2
134 
135 /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not
136  * group-related, so those indices are just 0 for S and 1 for NS.
137  * (If the CPU or the GIC, respectively, don't support the Security
138  * extensions then the S element is unused.)
139  */
140 #define GICV3_S 0
141 #define GICV3_NS 1
142 
143 typedef struct {
144     int irq;
145     uint8_t prio;
146     int grp;
147 } PendingIrq;
148 
149 struct GICv3CPUState {
150     GICv3State *gic;
151     CPUState *cpu;
152     qemu_irq parent_irq;
153     qemu_irq parent_fiq;
154     qemu_irq parent_virq;
155     qemu_irq parent_vfiq;
156 
157     /* Redistributor */
158     uint32_t level;                  /* Current IRQ level */
159     /* RD_base page registers */
160     uint32_t gicr_ctlr;
161     uint64_t gicr_typer;
162     uint32_t gicr_statusr[2];
163     uint32_t gicr_waker;
164     uint64_t gicr_propbaser;
165     uint64_t gicr_pendbaser;
166     /* SGI_base page registers */
167     uint32_t gicr_igroupr0;
168     uint32_t gicr_ienabler0;
169     uint32_t gicr_ipendr0;
170     uint32_t gicr_iactiver0;
171     uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
172     uint32_t gicr_igrpmodr0;
173     uint32_t gicr_nsacr;
174     uint8_t gicr_ipriorityr[GIC_INTERNAL];
175 
176     /* CPU interface */
177     uint64_t icc_sre_el1;
178     uint64_t icc_ctlr_el1[2];
179     uint64_t icc_pmr_el1;
180     uint64_t icc_bpr[3];
181     uint64_t icc_apr[3][4];
182     uint64_t icc_igrpen[3];
183     uint64_t icc_ctlr_el3;
184 
185     /* Virtualization control interface */
186     uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */
187     uint64_t ich_hcr_el2;
188     uint64_t ich_lr_el2[GICV3_LR_MAX];
189     uint64_t ich_vmcr_el2;
190 
191     /* Properties of the CPU interface. These are initialized from
192      * the settings in the CPU proper.
193      * If the number of implemented list registers is 0 then the
194      * virtualization support is not implemented.
195      */
196     int num_list_regs;
197     int vpribits; /* number of virtual priority bits */
198     int vprebits; /* number of virtual preemption bits */
199 
200     /* Current highest priority pending interrupt for this CPU.
201      * This is cached information that can be recalculated from the
202      * real state above; it doesn't need to be migrated.
203      */
204     PendingIrq hppi;
205     /* This is temporary working state, to avoid a malloc in gicv3_update() */
206     bool seenbetter;
207 };
208 
209 struct GICv3State {
210     /*< private >*/
211     SysBusDevice parent_obj;
212     /*< public >*/
213 
214     MemoryRegion iomem_dist; /* Distributor */
215     MemoryRegion *iomem_redist; /* Redistributor Regions */
216     uint32_t *redist_region_count; /* redistributor count within each region */
217     uint32_t nb_redist_regions; /* number of redist regions */
218 
219     uint32_t num_cpu;
220     uint32_t num_irq;
221     uint32_t revision;
222     bool security_extn;
223     bool irq_reset_nonsecure;
224     bool gicd_no_migration_shift_bug;
225 
226     int dev_fd; /* kvm device fd if backed by kvm vgic support */
227     Error *migration_blocker;
228 
229     /* Distributor */
230 
231     /* for a GIC with the security extensions the NS banked version of this
232      * register is just an alias of bit 1 of the S banked version.
233      */
234     uint32_t gicd_ctlr;
235     uint32_t gicd_statusr[2];
236     GIC_DECLARE_BITMAP(group);        /* GICD_IGROUPR */
237     GIC_DECLARE_BITMAP(grpmod);       /* GICD_IGRPMODR */
238     GIC_DECLARE_BITMAP(enabled);      /* GICD_ISENABLER */
239     GIC_DECLARE_BITMAP(pending);      /* GICD_ISPENDR */
240     GIC_DECLARE_BITMAP(active);       /* GICD_ISACTIVER */
241     GIC_DECLARE_BITMAP(level);        /* Current level */
242     GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */
243     uint8_t gicd_ipriority[GICV3_MAXIRQ];
244     uint64_t gicd_irouter[GICV3_MAXIRQ];
245     /* Cached information: pointer to the cpu i/f for the CPUs specified
246      * in the IROUTER registers
247      */
248     GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
249     uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
250 
251     GICv3CPUState *cpu;
252 };
253 
254 #define GICV3_BITMAP_ACCESSORS(BMP)                                     \
255     static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq)   \
256     {                                                                   \
257         gic_bmp_set_bit(irq, s->BMP);                                   \
258     }                                                                   \
259     static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq)   \
260     {                                                                   \
261         return gic_bmp_test_bit(irq, s->BMP);                           \
262     }                                                                   \
263     static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
264     {                                                                   \
265         gic_bmp_clear_bit(irq, s->BMP);                                 \
266     }                                                                   \
267     static inline void gicv3_gicd_##BMP##_replace(GICv3State *s,        \
268                                                   int irq, int value)   \
269     {                                                                   \
270         gic_bmp_replace_bit(irq, s->BMP, value);                        \
271     }
272 
273 GICV3_BITMAP_ACCESSORS(group)
274 GICV3_BITMAP_ACCESSORS(grpmod)
275 GICV3_BITMAP_ACCESSORS(enabled)
276 GICV3_BITMAP_ACCESSORS(pending)
277 GICV3_BITMAP_ACCESSORS(active)
278 GICV3_BITMAP_ACCESSORS(level)
279 GICV3_BITMAP_ACCESSORS(edge_trigger)
280 
281 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
282 typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
283 DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,
284                      ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON)
285 
286 struct ARMGICv3CommonClass {
287     /*< private >*/
288     SysBusDeviceClass parent_class;
289     /*< public >*/
290 
291     void (*pre_save)(GICv3State *s);
292     void (*post_load)(GICv3State *s);
293 };
294 
295 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
296                               const MemoryRegionOps *ops, Error **errp);
297 
298 #endif
299