1 /* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef HW_ARM_GIC_COMMON_H 22 #define HW_ARM_GIC_COMMON_H 23 24 #include "hw/sysbus.h" 25 26 /* Maximum number of possible interrupts, determined by the GIC architecture */ 27 #define GIC_MAXIRQ 1020 28 /* First 32 are private to each CPU (SGIs and PPIs). */ 29 #define GIC_INTERNAL 32 30 #define GIC_NR_SGIS 16 31 /* Maximum number of possible CPU interfaces, determined by GIC architecture */ 32 #define GIC_NCPU 8 33 34 #define MAX_NR_GROUP_PRIO 128 35 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) 36 37 typedef struct gic_irq_state { 38 /* The enable bits are only banked for per-cpu interrupts. */ 39 uint8_t enabled; 40 uint8_t pending; 41 uint8_t active; 42 uint8_t level; 43 bool model; /* 0 = N:N, 1 = 1:N */ 44 bool edge_trigger; /* true: edge-triggered, false: level-triggered */ 45 } gic_irq_state; 46 47 typedef struct GICState { 48 /*< private >*/ 49 SysBusDevice parent_obj; 50 /*< public >*/ 51 52 qemu_irq parent_irq[GIC_NCPU]; 53 bool enabled; 54 bool cpu_enabled[GIC_NCPU]; 55 56 gic_irq_state irq_state[GIC_MAXIRQ]; 57 uint8_t irq_target[GIC_MAXIRQ]; 58 uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; 59 uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; 60 uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; 61 /* For each SGI on the target CPU, we store 8 bits 62 * indicating which source CPUs have made this SGI 63 * pending on the target CPU. These correspond to 64 * the bytes in the GIC_SPENDSGIR* registers as 65 * read by the target CPU. 66 */ 67 uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU]; 68 69 uint16_t priority_mask[GIC_NCPU]; 70 uint16_t running_irq[GIC_NCPU]; 71 uint16_t running_priority[GIC_NCPU]; 72 uint16_t current_pending[GIC_NCPU]; 73 74 /* We present the GICv2 without security extensions to a guest and 75 * therefore the guest can configure the GICC_CTLR to configure group 1 76 * binary point in the abpr. 77 */ 78 uint8_t bpr[GIC_NCPU]; 79 uint8_t abpr[GIC_NCPU]; 80 81 /* The APR is implementation defined, so we choose a layout identical to 82 * the KVM ABI layout for QEMU's implementation of the gic: 83 * If an interrupt for preemption level X is active, then 84 * APRn[X mod 32] == 0b1, where n = X / 32 85 * otherwise the bit is clear. 86 * 87 * TODO: rewrite the interrupt acknowlege/complete routines to use 88 * the APR registers to track the necessary information to update 89 * s->running_priority[] on interrupt completion (ie completely remove 90 * last_active[][] and running_irq[]). This will be necessary if we ever 91 * want to support TCG<->KVM migration, or TCG guests which can 92 * do power management involving powering down and restarting 93 * the GIC. 94 */ 95 uint32_t apr[GIC_NR_APRS][GIC_NCPU]; 96 97 uint32_t num_cpu; 98 99 MemoryRegion iomem; /* Distributor */ 100 /* This is just so we can have an opaque pointer which identifies 101 * both this GIC and which CPU interface we should be accessing. 102 */ 103 struct GICState *backref[GIC_NCPU]; 104 MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ 105 uint32_t num_irq; 106 uint32_t revision; 107 int dev_fd; /* kvm device fd if backed by kvm vgic support */ 108 } GICState; 109 110 #define TYPE_ARM_GIC_COMMON "arm_gic_common" 111 #define ARM_GIC_COMMON(obj) \ 112 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON) 113 #define ARM_GIC_COMMON_CLASS(klass) \ 114 OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON) 115 #define ARM_GIC_COMMON_GET_CLASS(obj) \ 116 OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON) 117 118 typedef struct ARMGICCommonClass { 119 /*< private >*/ 120 SysBusDeviceClass parent_class; 121 /*< public >*/ 122 123 void (*pre_save)(GICState *s); 124 void (*post_load)(GICState *s); 125 } ARMGICCommonClass; 126 127 #endif 128