xref: /openbmc/qemu/include/hw/intc/arm_gic_common.h (revision 4a09d0bb)
1 /*
2  * ARM GIC support
3  *
4  * Copyright (c) 2012 Linaro Limited
5  * Written by Peter Maydell
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation, either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #ifndef HW_ARM_GIC_COMMON_H
22 #define HW_ARM_GIC_COMMON_H
23 
24 #include "hw/sysbus.h"
25 
26 /* Maximum number of possible interrupts, determined by the GIC architecture */
27 #define GIC_MAXIRQ 1020
28 /* First 32 are private to each CPU (SGIs and PPIs). */
29 #define GIC_INTERNAL 32
30 #define GIC_NR_SGIS 16
31 /* Maximum number of possible CPU interfaces, determined by GIC architecture */
32 #define GIC_NCPU 8
33 
34 #define MAX_NR_GROUP_PRIO 128
35 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
36 
37 #define GIC_MIN_BPR 0
38 #define GIC_MIN_ABPR (GIC_MIN_BPR + 1)
39 
40 typedef struct gic_irq_state {
41     /* The enable bits are only banked for per-cpu interrupts.  */
42     uint8_t enabled;
43     uint8_t pending;
44     uint8_t active;
45     uint8_t level;
46     bool model; /* 0 = N:N, 1 = 1:N */
47     bool edge_trigger; /* true: edge-triggered, false: level-triggered  */
48     uint8_t group;
49 } gic_irq_state;
50 
51 typedef struct GICState {
52     /*< private >*/
53     SysBusDevice parent_obj;
54     /*< public >*/
55 
56     qemu_irq parent_irq[GIC_NCPU];
57     qemu_irq parent_fiq[GIC_NCPU];
58     qemu_irq parent_virq[GIC_NCPU];
59     qemu_irq parent_vfiq[GIC_NCPU];
60     /* GICD_CTLR; for a GIC with the security extensions the NS banked version
61      * of this register is just an alias of bit 1 of the S banked version.
62      */
63     uint32_t ctlr;
64     /* GICC_CTLR; again, the NS banked version is just aliases of bits of
65      * the S banked register, so our state only needs to store the S version.
66      */
67     uint32_t cpu_ctlr[GIC_NCPU];
68 
69     gic_irq_state irq_state[GIC_MAXIRQ];
70     uint8_t irq_target[GIC_MAXIRQ];
71     uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
72     uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
73     /* For each SGI on the target CPU, we store 8 bits
74      * indicating which source CPUs have made this SGI
75      * pending on the target CPU. These correspond to
76      * the bytes in the GIC_SPENDSGIR* registers as
77      * read by the target CPU.
78      */
79     uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
80 
81     uint16_t priority_mask[GIC_NCPU];
82     uint16_t running_priority[GIC_NCPU];
83     uint16_t current_pending[GIC_NCPU];
84 
85     /* If we present the GICv2 without security extensions to a guest,
86      * the guest can configure the GICC_CTLR to configure group 1 binary point
87      * in the abpr.
88      * For a GIC with Security Extensions we use use bpr for the
89      * secure copy and abpr as storage for the non-secure copy of the register.
90      */
91     uint8_t  bpr[GIC_NCPU];
92     uint8_t  abpr[GIC_NCPU];
93 
94     /* The APR is implementation defined, so we choose a layout identical to
95      * the KVM ABI layout for QEMU's implementation of the gic:
96      * If an interrupt for preemption level X is active, then
97      *   APRn[X mod 32] == 0b1,  where n = X / 32
98      * otherwise the bit is clear.
99      */
100     uint32_t apr[GIC_NR_APRS][GIC_NCPU];
101     uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
102 
103     uint32_t num_cpu;
104 
105     MemoryRegion iomem; /* Distributor */
106     /* This is just so we can have an opaque pointer which identifies
107      * both this GIC and which CPU interface we should be accessing.
108      */
109     struct GICState *backref[GIC_NCPU];
110     MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
111     uint32_t num_irq;
112     uint32_t revision;
113     bool security_extn;
114     bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
115     int dev_fd; /* kvm device fd if backed by kvm vgic support */
116     Error *migration_blocker;
117 } GICState;
118 
119 #define TYPE_ARM_GIC_COMMON "arm_gic_common"
120 #define ARM_GIC_COMMON(obj) \
121      OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
122 #define ARM_GIC_COMMON_CLASS(klass) \
123      OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
124 #define ARM_GIC_COMMON_GET_CLASS(obj) \
125      OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
126 
127 typedef struct ARMGICCommonClass {
128     /*< private >*/
129     SysBusDeviceClass parent_class;
130     /*< public >*/
131 
132     void (*pre_save)(GICState *s);
133     void (*post_load)(GICState *s);
134 } ARMGICCommonClass;
135 
136 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
137                             const MemoryRegionOps *ops);
138 
139 #endif
140