1 /* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef HW_ARM_GIC_COMMON_H 22 #define HW_ARM_GIC_COMMON_H 23 24 #include "hw/sysbus.h" 25 26 /* Maximum number of possible interrupts, determined by the GIC architecture */ 27 #define GIC_MAXIRQ 1020 28 /* First 32 are private to each CPU (SGIs and PPIs). */ 29 #define GIC_INTERNAL 32 30 /* Maximum number of possible CPU interfaces, determined by GIC architecture */ 31 #define GIC_NCPU 8 32 33 typedef struct gic_irq_state { 34 /* The enable bits are only banked for per-cpu interrupts. */ 35 uint8_t enabled; 36 uint8_t pending; 37 uint8_t active; 38 uint8_t level; 39 bool model; /* 0 = N:N, 1 = 1:N */ 40 bool trigger; /* nonzero = edge triggered. */ 41 } gic_irq_state; 42 43 typedef struct GICState { 44 /*< private >*/ 45 SysBusDevice parent_obj; 46 /*< public >*/ 47 48 qemu_irq parent_irq[GIC_NCPU]; 49 bool enabled; 50 bool cpu_enabled[GIC_NCPU]; 51 52 gic_irq_state irq_state[GIC_MAXIRQ]; 53 uint8_t irq_target[GIC_MAXIRQ]; 54 uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; 55 uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; 56 uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; 57 58 uint16_t priority_mask[GIC_NCPU]; 59 uint16_t running_irq[GIC_NCPU]; 60 uint16_t running_priority[GIC_NCPU]; 61 uint16_t current_pending[GIC_NCPU]; 62 63 uint32_t num_cpu; 64 65 MemoryRegion iomem; /* Distributor */ 66 /* This is just so we can have an opaque pointer which identifies 67 * both this GIC and which CPU interface we should be accessing. 68 */ 69 struct GICState *backref[GIC_NCPU]; 70 MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ 71 uint32_t num_irq; 72 uint32_t revision; 73 } GICState; 74 75 #define TYPE_ARM_GIC_COMMON "arm_gic_common" 76 #define ARM_GIC_COMMON(obj) \ 77 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON) 78 #define ARM_GIC_COMMON_CLASS(klass) \ 79 OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON) 80 #define ARM_GIC_COMMON_GET_CLASS(obj) \ 81 OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON) 82 83 typedef struct ARMGICCommonClass { 84 /*< private >*/ 85 SysBusDeviceClass parent_class; 86 /*< public >*/ 87 88 void (*pre_save)(GICState *s); 89 void (*post_load)(GICState *s); 90 } ARMGICCommonClass; 91 92 #endif 93