xref: /openbmc/qemu/include/hw/input/i8042.h (revision c9849a71)
1 /*
2  * QEMU PS/2 Controller
3  *
4  * Copyright (c) 2003 Fabrice Bellard
5  *
6  * SPDX-License-Identifier: MIT
7  */
8 #ifndef HW_INPUT_I8042_H
9 #define HW_INPUT_I8042_H
10 
11 #include "hw/isa/isa.h"
12 #include "qom/object.h"
13 
14 typedef struct KBDState {
15     uint8_t write_cmd; /* if non zero, write data to port 60 is expected */
16     uint8_t status;
17     uint8_t mode;
18     uint8_t outport;
19     uint32_t migration_flags;
20     uint32_t obsrc;
21     bool outport_present;
22     bool extended_state;
23     bool extended_state_loaded;
24     /* Bitmask of devices with data available.  */
25     uint8_t pending;
26     uint8_t obdata;
27     uint8_t cbdata;
28     uint8_t pending_tmp;
29     void *kbd;
30     void *mouse;
31     QEMUTimer *throttle_timer;
32 
33     qemu_irq irq_kbd;
34     qemu_irq irq_mouse;
35     qemu_irq a20_out;
36     hwaddr mask;
37 } KBDState;
38 
39 #define TYPE_I8042 "i8042"
40 OBJECT_DECLARE_SIMPLE_TYPE(ISAKBDState, I8042)
41 
42 struct ISAKBDState {
43     ISADevice parent_obj;
44 
45     KBDState kbd;
46     bool kbd_throttle;
47     MemoryRegion io[2];
48     uint8_t kbd_irq;
49     uint8_t mouse_irq;
50 };
51 
52 #define I8042_A20_LINE "a20"
53 
54 
55 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
56                    MemoryRegion *region, ram_addr_t size,
57                    hwaddr mask);
58 void i8042_isa_mouse_fake_event(ISAKBDState *isa);
59 void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out);
60 
61 static inline bool i8042_present(void)
62 {
63     bool amb = false;
64     return object_resolve_path_type("", TYPE_I8042, &amb) || amb;
65 }
66 
67 /*
68  * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
69  * Flags, bit offset 1 - 8042.
70  */
71 static inline uint16_t iapc_boot_arch_8042(void)
72 {
73     return i8042_present() ? 0x1 << 1 : 0x0 ;
74 }
75 
76 #endif /* HW_INPUT_I8042_H */
77