1 /* 2 * QEMU PS/2 Controller 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * SPDX-License-Identifier: MIT 7 */ 8 #ifndef HW_INPUT_I8042_H 9 #define HW_INPUT_I8042_H 10 11 #include "hw/isa/isa.h" 12 #include "hw/sysbus.h" 13 #include "qom/object.h" 14 15 typedef struct KBDState { 16 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */ 17 uint8_t status; 18 uint8_t mode; 19 uint8_t outport; 20 uint32_t migration_flags; 21 uint32_t obsrc; 22 bool outport_present; 23 bool extended_state; 24 bool extended_state_loaded; 25 /* Bitmask of devices with data available. */ 26 uint8_t pending; 27 uint8_t obdata; 28 uint8_t cbdata; 29 uint8_t pending_tmp; 30 void *kbd; 31 void *mouse; 32 QEMUTimer *throttle_timer; 33 34 qemu_irq irq_kbd; 35 qemu_irq irq_mouse; 36 qemu_irq a20_out; 37 hwaddr mask; 38 } KBDState; 39 40 #define TYPE_I8042 "i8042" 41 OBJECT_DECLARE_SIMPLE_TYPE(ISAKBDState, I8042) 42 43 struct ISAKBDState { 44 ISADevice parent_obj; 45 46 KBDState kbd; 47 bool kbd_throttle; 48 MemoryRegion io[2]; 49 uint8_t kbd_irq; 50 uint8_t mouse_irq; 51 }; 52 53 #define TYPE_I8042_MMIO "i8042-mmio" 54 OBJECT_DECLARE_SIMPLE_TYPE(MMIOKBDState, I8042_MMIO) 55 56 struct MMIOKBDState { 57 SysBusDevice parent_obj; 58 59 KBDState kbd; 60 uint32_t size; 61 }; 62 63 #define I8042_A20_LINE "a20" 64 65 66 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 67 MemoryRegion *region, ram_addr_t size, 68 hwaddr mask); 69 void i8042_isa_mouse_fake_event(ISAKBDState *isa); 70 void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out); 71 72 static inline bool i8042_present(void) 73 { 74 bool amb = false; 75 return object_resolve_path_type("", TYPE_I8042, &amb) || amb; 76 } 77 78 /* 79 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 80 * Flags, bit offset 1 - 8042. 81 */ 82 static inline uint16_t iapc_boot_arch_8042(void) 83 { 84 return i8042_present() ? 0x1 << 1 : 0x0 ; 85 } 86 87 #endif /* HW_INPUT_I8042_H */ 88