1 /* 2 * QEMU PS/2 Controller 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * SPDX-License-Identifier: MIT 7 */ 8 #ifndef HW_INPUT_I8042_H 9 #define HW_INPUT_I8042_H 10 11 #include "hw/isa/isa.h" 12 #include "hw/sysbus.h" 13 #include "qom/object.h" 14 15 #define I8042_KBD_IRQ 0 16 #define I8042_MOUSE_IRQ 1 17 18 typedef struct KBDState { 19 uint8_t write_cmd; /* if non zero, write data to port 60 is expected */ 20 uint8_t status; 21 uint8_t mode; 22 uint8_t outport; 23 uint32_t migration_flags; 24 uint32_t obsrc; 25 bool outport_present; 26 bool extended_state; 27 bool extended_state_loaded; 28 /* Bitmask of devices with data available. */ 29 uint8_t pending; 30 uint8_t obdata; 31 uint8_t cbdata; 32 uint8_t pending_tmp; 33 void *kbd; 34 void *mouse; 35 QEMUTimer *throttle_timer; 36 37 qemu_irq irqs[2]; 38 qemu_irq a20_out; 39 hwaddr mask; 40 } KBDState; 41 42 #define TYPE_I8042 "i8042" 43 OBJECT_DECLARE_SIMPLE_TYPE(ISAKBDState, I8042) 44 45 struct ISAKBDState { 46 ISADevice parent_obj; 47 48 KBDState kbd; 49 bool kbd_throttle; 50 MemoryRegion io[2]; 51 uint8_t kbd_irq; 52 uint8_t mouse_irq; 53 }; 54 55 /* 56 * QEMU interface: 57 * + sysbus MMIO region 0: MemoryRegion defining the command/status/data 58 * registers (access determined by mask property and access type) 59 * + Named GPIO input "ps2-kbd-input-irq": set to 1 if the downstream PS2 60 * keyboard device has asserted its irq 61 * + Named GPIO input "ps2-mouse-input-irq": set to 1 if the downstream PS2 62 * mouse device has asserted its irq 63 * + Unnamed GPIO output 0-1: i8042 output irqs for keyboard (0) or mouse (1) 64 */ 65 66 #define TYPE_I8042_MMIO "i8042-mmio" 67 OBJECT_DECLARE_SIMPLE_TYPE(MMIOKBDState, I8042_MMIO) 68 69 struct MMIOKBDState { 70 SysBusDevice parent_obj; 71 72 KBDState kbd; 73 uint32_t size; 74 MemoryRegion region; 75 }; 76 77 #define I8042_A20_LINE "a20" 78 79 80 MMIOKBDState *i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 81 ram_addr_t size, hwaddr mask); 82 void i8042_isa_mouse_fake_event(ISAKBDState *isa); 83 void i8042_setup_a20_line(ISADevice *dev, qemu_irq a20_out); 84 85 static inline bool i8042_present(void) 86 { 87 bool amb = false; 88 return object_resolve_path_type("", TYPE_I8042, &amb) || amb; 89 } 90 91 /* 92 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture 93 * Flags, bit offset 1 - 8042. 94 */ 95 static inline uint16_t iapc_boot_arch_8042(void) 96 { 97 return i8042_present() ? 0x1 << 1 : 0x0 ; 98 } 99 100 #endif /* HW_INPUT_I8042_H */ 101