1 /* 2 * Copyright (c) 2019 Red Hat, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2 or later, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef HW_I386_X86_H 18 #define HW_I386_X86_H 19 20 #include "exec/hwaddr.h" 21 #include "exec/memory.h" 22 23 #include "hw/boards.h" 24 #include "hw/intc/ioapic.h" 25 #include "hw/isa/isa.h" 26 #include "qom/object.h" 27 28 struct X86MachineClass { 29 /*< private >*/ 30 MachineClass parent; 31 32 /*< public >*/ 33 34 /* TSC rate migration: */ 35 bool save_tsc_khz; 36 /* use DMA capable linuxboot option rom */ 37 bool fwcfg_dma_enabled; 38 /* CPU and apic information: */ 39 bool apic_xrupt_override; 40 }; 41 42 struct X86MachineState { 43 /*< private >*/ 44 MachineState parent; 45 46 /*< public >*/ 47 48 /* Pointers to devices and objects: */ 49 ISADevice *rtc; 50 FWCfgState *fw_cfg; 51 qemu_irq *gsi; 52 DeviceState *ioapic2; 53 GMappedFile *initrd_mapped_file; 54 HotplugHandler *acpi_dev; 55 56 /* 57 * Map the whole BIOS just underneath the 4 GiB address boundary. Only used 58 * in the ROM (-bios) case. 59 */ 60 MemoryRegion bios; 61 62 /* 63 * Map the upper 128 KiB of the BIOS just underneath the 1 MiB address 64 * boundary. 65 */ 66 MemoryRegion isa_bios; 67 68 /* RAM information (sizes, addresses, configuration): */ 69 ram_addr_t below_4g_mem_size, above_4g_mem_size; 70 71 /* Start address of the initial RAM above 4G */ 72 uint64_t above_4g_mem_start; 73 74 /* CPU and apic information: */ 75 unsigned pci_irq_mask; 76 unsigned apic_id_limit; 77 uint16_t boot_cpus; 78 SgxEPCList *sgx_epc_list; 79 80 OnOffAuto smm; 81 OnOffAuto acpi; 82 OnOffAuto pit; 83 OnOffAuto pic; 84 85 char *oem_id; 86 char *oem_table_id; 87 /* 88 * Address space used by IOAPIC device. All IOAPIC interrupts 89 * will be translated to MSI messages in the address space. 90 */ 91 AddressSpace *ioapic_as; 92 93 /* 94 * Ratelimit enforced on detected bus locks in guest. 95 * The default value of the bus_lock_ratelimit is 0 per second, 96 * which means no limitation on the guest's bus locks. 97 */ 98 uint64_t bus_lock_ratelimit; 99 }; 100 101 #define X86_MACHINE_SMM "smm" 102 #define X86_MACHINE_ACPI "acpi" 103 #define X86_MACHINE_PIT "pit" 104 #define X86_MACHINE_PIC "pic" 105 #define X86_MACHINE_OEM_ID "x-oem-id" 106 #define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id" 107 #define X86_MACHINE_BUS_LOCK_RATELIMIT "bus-lock-ratelimit" 108 109 #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86") 110 OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE) 111 112 uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms, 113 unsigned int cpu_index); 114 115 void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp); 116 void x86_cpus_init(X86MachineState *pcms, int default_cpu_version); 117 CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms, 118 unsigned cpu_index); 119 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx); 120 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms); 121 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx); 122 void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count); 123 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, 124 DeviceState *dev, Error **errp); 125 void x86_cpu_plug(HotplugHandler *hotplug_dev, 126 DeviceState *dev, Error **errp); 127 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 128 DeviceState *dev, Error **errp); 129 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, 130 DeviceState *dev, Error **errp); 131 132 void x86_isa_bios_init(MemoryRegion *isa_bios, MemoryRegion *isa_memory, 133 MemoryRegion *bios, bool read_only); 134 void x86_bios_rom_init(X86MachineState *x86ms, const char *default_firmware, 135 MemoryRegion *rom_memory, bool isapc_ram_fw); 136 137 void x86_load_linux(X86MachineState *x86ms, 138 FWCfgState *fw_cfg, 139 int acpi_data_size, 140 bool pvh_enabled); 141 142 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms); 143 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms); 144 145 /* Global System Interrupts */ 146 147 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 148 149 typedef struct GSIState { 150 qemu_irq i8259_irq[ISA_NUM_IRQS]; 151 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 152 qemu_irq ioapic2_irq[IOAPIC_NUM_PINS]; 153 } GSIState; 154 155 qemu_irq x86_allocate_cpu_irq(void); 156 void gsi_handler(void *opaque, int n, int level); 157 void ioapic_init_gsi(GSIState *gsi_state, Object *parent); 158 DeviceState *ioapic_init_secondary(GSIState *gsi_state); 159 160 /* pc_sysfw.c */ 161 void x86_firmware_configure(void *ptr, int size); 162 163 #endif 164