1 /* 2 * Copyright (c) 2019 Red Hat, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2 or later, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef HW_I386_X86_H 18 #define HW_I386_X86_H 19 20 #include "qemu-common.h" 21 #include "exec/hwaddr.h" 22 #include "qemu/notify.h" 23 24 #include "hw/i386/topology.h" 25 #include "hw/boards.h" 26 #include "hw/nmi.h" 27 #include "hw/isa/isa.h" 28 #include "hw/i386/ioapic.h" 29 #include "qom/object.h" 30 31 struct X86MachineClass { 32 /*< private >*/ 33 MachineClass parent; 34 35 /*< public >*/ 36 37 /* TSC rate migration: */ 38 bool save_tsc_khz; 39 /* Enables contiguous-apic-ID mode */ 40 bool compat_apic_id_mode; 41 }; 42 typedef struct X86MachineClass X86MachineClass; 43 44 struct X86MachineState { 45 /*< private >*/ 46 MachineState parent; 47 48 /*< public >*/ 49 50 /* Pointers to devices and objects: */ 51 ISADevice *rtc; 52 FWCfgState *fw_cfg; 53 qemu_irq *gsi; 54 GMappedFile *initrd_mapped_file; 55 56 /* RAM information (sizes, addresses, configuration): */ 57 ram_addr_t below_4g_mem_size, above_4g_mem_size; 58 59 /* CPU and apic information: */ 60 bool apic_xrupt_override; 61 unsigned apic_id_limit; 62 uint16_t boot_cpus; 63 unsigned smp_dies; 64 65 OnOffAuto smm; 66 OnOffAuto acpi; 67 68 /* 69 * Address space used by IOAPIC device. All IOAPIC interrupts 70 * will be translated to MSI messages in the address space. 71 */ 72 AddressSpace *ioapic_as; 73 }; 74 typedef struct X86MachineState X86MachineState; 75 76 #define X86_MACHINE_SMM "smm" 77 #define X86_MACHINE_ACPI "acpi" 78 79 #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86") 80 DECLARE_OBJ_CHECKERS(X86MachineState, X86MachineClass, 81 X86_MACHINE, TYPE_X86_MACHINE) 82 83 void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms); 84 85 uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms, 86 unsigned int cpu_index); 87 88 void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp); 89 void x86_cpus_init(X86MachineState *pcms, int default_cpu_version); 90 CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms, 91 unsigned cpu_index); 92 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx); 93 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms); 94 95 void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw); 96 97 void x86_load_linux(X86MachineState *x86ms, 98 FWCfgState *fw_cfg, 99 int acpi_data_size, 100 bool pvh_enabled, 101 bool linuxboot_dma_enabled); 102 103 bool x86_machine_is_smm_enabled(X86MachineState *x86ms); 104 bool x86_machine_is_acpi_enabled(X86MachineState *x86ms); 105 106 /* Global System Interrupts */ 107 108 #define GSI_NUM_PINS IOAPIC_NUM_PINS 109 110 typedef struct GSIState { 111 qemu_irq i8259_irq[ISA_NUM_IRQS]; 112 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 113 } GSIState; 114 115 qemu_irq x86_allocate_cpu_irq(void); 116 void gsi_handler(void *opaque, int n, int level); 117 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 118 119 /* hpet.c */ 120 extern int no_hpet; 121 122 #endif 123